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This patch adds DT binding documentation for Exynos4415 SoC system clock controllers. Signed-off-by: Chanwoo Choi <cw00.choi@samsung.com> Acked-by: Kyungmin Park <kyungmin.park@samsung.com> Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com>
39 lines
1.2 KiB
Plaintext
39 lines
1.2 KiB
Plaintext
* Samsung Exynos4415 Clock Controller
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The Exynos4415 clock controller generates and supplies clock to various
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consumer devices within the Exynos4415 SoC.
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Required properties:
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- compatible: should be one of the following:
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- "samsung,exynos4415-cmu" - for the main system clocks controller
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(CMU_LEFTBUS, CMU_RIGHTBUS, CMU_TOP, CMU_CPU clock domains).
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- "samsung,exynos4415-cmu-dmc" - for the Exynos4415 SoC DRAM Memory
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Controller (DMC) domain clock controller.
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- reg: physical base address of the controller and length of memory mapped
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region.
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- #clock-cells: should be 1.
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Each clock is assigned an identifier and client nodes can use this identifier
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to specify the clock which they consume.
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All available clocks are defined as preprocessor macros in
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dt-bindings/clock/exynos4415.h header and can be used in device
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tree sources.
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Example 1: An example of a clock controller node is listed below.
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cmu: clock-controller@10030000 {
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compatible = "samsung,exynos4415-cmu";
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reg = <0x10030000 0x18000>;
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#clock-cells = <1>;
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};
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cmu-dmc: clock-controller@105C0000 {
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compatible = "samsung,exynos4415-cmu-dmc";
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reg = <0x105C0000 0x3000>;
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#clock-cells = <1>;
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};
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