mirror of
https://github.com/torvalds/linux.git
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8f574b35f2
Add AR8151 v2.0 Gigabit 1000 support
Change jumbo frame size to 6K
Update L0s/L1 rountine
when link speed is 100M or 1G, set L1 link timer to 4 for l1d_2 and l2c_b2
set L1 link timer to 7 for l2c_b, set L1 link timer to 0xF for others.
Update atl1c_suspend routine
just refactory the function, add atl1c_phy_power_saving routine,
when Wake On Lan enable, this func will be called to save power,
it will reautoneg PHY to 10/100M speed depend on the link
partners link capability.
Update atl1c_configure_des_ring
do not use l2c_b default SRAM configuration.
Signed-off-by: Jie Yang <Jie.Yang@atheros.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
641 lines
21 KiB
C
641 lines
21 KiB
C
/*
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* Copyright(c) 2008 - 2009 Atheros Corporation. All rights reserved.
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*
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* Derived from Intel e1000 driver
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* Copyright(c) 1999 - 2005 Intel Corporation. All rights reserved.
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of the GNU General Public License as published by the Free
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* Software Foundation; either version 2 of the License, or (at your option)
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* any later version.
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*
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* This program is distributed in the hope that it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* more details.
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*
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* You should have received a copy of the GNU General Public License along with
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* this program; if not, write to the Free Software Foundation, Inc., 59
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* Temple Place - Suite 330, Boston, MA 02111-1307, USA.
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*/
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#ifndef _ATL1C_H_
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#define _ATL1C_H_
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#include <linux/version.h>
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#include <linux/init.h>
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#include <linux/types.h>
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#include <linux/errno.h>
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#include <linux/module.h>
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#include <linux/pci.h>
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#include <linux/netdevice.h>
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#include <linux/etherdevice.h>
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#include <linux/skbuff.h>
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#include <linux/ioport.h>
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#include <linux/slab.h>
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#include <linux/list.h>
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#include <linux/delay.h>
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#include <linux/sched.h>
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#include <linux/in.h>
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#include <linux/ip.h>
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#include <linux/ipv6.h>
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#include <linux/udp.h>
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#include <linux/mii.h>
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#include <linux/io.h>
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#include <linux/vmalloc.h>
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#include <linux/pagemap.h>
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#include <linux/tcp.h>
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#include <linux/ethtool.h>
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#include <linux/if_vlan.h>
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#include <linux/workqueue.h>
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#include <net/checksum.h>
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#include <net/ip6_checksum.h>
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#include "atl1c_hw.h"
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/* Wake Up Filter Control */
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#define AT_WUFC_LNKC 0x00000001 /* Link Status Change Wakeup Enable */
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#define AT_WUFC_MAG 0x00000002 /* Magic Packet Wakeup Enable */
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#define AT_WUFC_EX 0x00000004 /* Directed Exact Wakeup Enable */
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#define AT_WUFC_MC 0x00000008 /* Multicast Wakeup Enable */
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#define AT_WUFC_BC 0x00000010 /* Broadcast Wakeup Enable */
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#define AT_VLAN_TO_TAG(_vlan, _tag) \
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_tag = ((((_vlan) >> 8) & 0xFF) |\
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(((_vlan) & 0xFF) << 8))
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#define AT_TAG_TO_VLAN(_tag, _vlan) \
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_vlan = ((((_tag) >> 8) & 0xFF) |\
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(((_tag) & 0xFF) << 8))
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#define SPEED_0 0xffff
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#define HALF_DUPLEX 1
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#define FULL_DUPLEX 2
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#define AT_RX_BUF_SIZE (ETH_FRAME_LEN + VLAN_HLEN + ETH_FCS_LEN)
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#define MAX_JUMBO_FRAME_SIZE (6*1024)
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#define MAX_TSO_FRAME_SIZE (7*1024)
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#define MAX_TX_OFFLOAD_THRESH (9*1024)
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#define AT_MAX_RECEIVE_QUEUE 4
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#define AT_DEF_RECEIVE_QUEUE 1
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#define AT_MAX_TRANSMIT_QUEUE 2
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#define AT_DMA_HI_ADDR_MASK 0xffffffff00000000ULL
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#define AT_DMA_LO_ADDR_MASK 0x00000000ffffffffULL
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#define AT_TX_WATCHDOG (5 * HZ)
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#define AT_MAX_INT_WORK 5
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#define AT_TWSI_EEPROM_TIMEOUT 100
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#define AT_HW_MAX_IDLE_DELAY 10
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#define AT_SUSPEND_LINK_TIMEOUT 100
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#define AT_ASPM_L0S_TIMER 6
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#define AT_ASPM_L1_TIMER 12
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#define AT_LCKDET_TIMER 12
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#define ATL1C_PCIE_L0S_L1_DISABLE 0x01
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#define ATL1C_PCIE_PHY_RESET 0x02
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#define ATL1C_ASPM_L0s_ENABLE 0x0001
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#define ATL1C_ASPM_L1_ENABLE 0x0002
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#define AT_REGS_LEN (75 * sizeof(u32))
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#define AT_EEPROM_LEN 512
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#define ATL1C_GET_DESC(R, i, type) (&(((type *)((R)->desc))[i]))
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#define ATL1C_RFD_DESC(R, i) ATL1C_GET_DESC(R, i, struct atl1c_rx_free_desc)
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#define ATL1C_TPD_DESC(R, i) ATL1C_GET_DESC(R, i, struct atl1c_tpd_desc)
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#define ATL1C_RRD_DESC(R, i) ATL1C_GET_DESC(R, i, struct atl1c_recv_ret_status)
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/* tpd word 1 bit 0:7 General Checksum task offload */
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#define TPD_L4HDR_OFFSET_MASK 0x00FF
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#define TPD_L4HDR_OFFSET_SHIFT 0
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/* tpd word 1 bit 0:7 Large Send task offload (IPv4/IPV6) */
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#define TPD_TCPHDR_OFFSET_MASK 0x00FF
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#define TPD_TCPHDR_OFFSET_SHIFT 0
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/* tpd word 1 bit 0:7 Custom Checksum task offload */
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#define TPD_PLOADOFFSET_MASK 0x00FF
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#define TPD_PLOADOFFSET_SHIFT 0
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/* tpd word 1 bit 8:17 */
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#define TPD_CCSUM_EN_MASK 0x0001
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#define TPD_CCSUM_EN_SHIFT 8
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#define TPD_IP_CSUM_MASK 0x0001
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#define TPD_IP_CSUM_SHIFT 9
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#define TPD_TCP_CSUM_MASK 0x0001
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#define TPD_TCP_CSUM_SHIFT 10
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#define TPD_UDP_CSUM_MASK 0x0001
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#define TPD_UDP_CSUM_SHIFT 11
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#define TPD_LSO_EN_MASK 0x0001 /* TCP Large Send Offload */
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#define TPD_LSO_EN_SHIFT 12
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#define TPD_LSO_VER_MASK 0x0001
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#define TPD_LSO_VER_SHIFT 13 /* 0 : ipv4; 1 : ipv4/ipv6 */
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#define TPD_CON_VTAG_MASK 0x0001
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#define TPD_CON_VTAG_SHIFT 14
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#define TPD_INS_VTAG_MASK 0x0001
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#define TPD_INS_VTAG_SHIFT 15
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#define TPD_IPV4_PACKET_MASK 0x0001 /* valid when LSO VER is 1 */
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#define TPD_IPV4_PACKET_SHIFT 16
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#define TPD_ETH_TYPE_MASK 0x0001
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#define TPD_ETH_TYPE_SHIFT 17 /* 0 : 802.3 frame; 1 : Ethernet */
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/* tpd word 18:25 Custom Checksum task offload */
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#define TPD_CCSUM_OFFSET_MASK 0x00FF
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#define TPD_CCSUM_OFFSET_SHIFT 18
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#define TPD_CCSUM_EPAD_MASK 0x0001
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#define TPD_CCSUM_EPAD_SHIFT 30
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/* tpd word 18:30 Large Send task offload (IPv4/IPV6) */
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#define TPD_MSS_MASK 0x1FFF
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#define TPD_MSS_SHIFT 18
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#define TPD_EOP_MASK 0x0001
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#define TPD_EOP_SHIFT 31
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struct atl1c_tpd_desc {
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__le16 buffer_len; /* include 4-byte CRC */
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__le16 vlan_tag;
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__le32 word1;
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__le64 buffer_addr;
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};
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struct atl1c_tpd_ext_desc {
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u32 reservd_0;
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__le32 word1;
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__le32 pkt_len;
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u32 reservd_1;
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};
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/* rrs word 0 bit 0:31 */
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#define RRS_RX_CSUM_MASK 0xFFFF
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#define RRS_RX_CSUM_SHIFT 0
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#define RRS_RX_RFD_CNT_MASK 0x000F
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#define RRS_RX_RFD_CNT_SHIFT 16
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#define RRS_RX_RFD_INDEX_MASK 0x0FFF
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#define RRS_RX_RFD_INDEX_SHIFT 20
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/* rrs flag bit 0:16 */
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#define RRS_HEAD_LEN_MASK 0x00FF
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#define RRS_HEAD_LEN_SHIFT 0
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#define RRS_HDS_TYPE_MASK 0x0003
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#define RRS_HDS_TYPE_SHIFT 8
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#define RRS_CPU_NUM_MASK 0x0003
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#define RRS_CPU_NUM_SHIFT 10
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#define RRS_HASH_FLG_MASK 0x000F
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#define RRS_HASH_FLG_SHIFT 12
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#define RRS_HDS_TYPE_HEAD 1
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#define RRS_HDS_TYPE_DATA 2
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#define RRS_IS_NO_HDS_TYPE(flag) \
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((((flag) >> (RRS_HDS_TYPE_SHIFT)) & RRS_HDS_TYPE_MASK) == 0)
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#define RRS_IS_HDS_HEAD(flag) \
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((((flag) >> (RRS_HDS_TYPE_SHIFT)) & RRS_HDS_TYPE_MASK) == \
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RRS_HDS_TYPE_HEAD)
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#define RRS_IS_HDS_DATA(flag) \
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((((flag) >> (RRS_HDS_TYPE_SHIFT)) & RRS_HDS_TYPE_MASK) == \
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RRS_HDS_TYPE_DATA)
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/* rrs word 3 bit 0:31 */
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#define RRS_PKT_SIZE_MASK 0x3FFF
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#define RRS_PKT_SIZE_SHIFT 0
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#define RRS_ERR_L4_CSUM_MASK 0x0001
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#define RRS_ERR_L4_CSUM_SHIFT 14
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#define RRS_ERR_IP_CSUM_MASK 0x0001
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#define RRS_ERR_IP_CSUM_SHIFT 15
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#define RRS_VLAN_INS_MASK 0x0001
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#define RRS_VLAN_INS_SHIFT 16
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#define RRS_PROT_ID_MASK 0x0007
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#define RRS_PROT_ID_SHIFT 17
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#define RRS_RX_ERR_SUM_MASK 0x0001
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#define RRS_RX_ERR_SUM_SHIFT 20
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#define RRS_RX_ERR_CRC_MASK 0x0001
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#define RRS_RX_ERR_CRC_SHIFT 21
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#define RRS_RX_ERR_FAE_MASK 0x0001
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#define RRS_RX_ERR_FAE_SHIFT 22
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#define RRS_RX_ERR_TRUNC_MASK 0x0001
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#define RRS_RX_ERR_TRUNC_SHIFT 23
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#define RRS_RX_ERR_RUNC_MASK 0x0001
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#define RRS_RX_ERR_RUNC_SHIFT 24
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#define RRS_RX_ERR_ICMP_MASK 0x0001
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#define RRS_RX_ERR_ICMP_SHIFT 25
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#define RRS_PACKET_BCAST_MASK 0x0001
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#define RRS_PACKET_BCAST_SHIFT 26
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#define RRS_PACKET_MCAST_MASK 0x0001
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#define RRS_PACKET_MCAST_SHIFT 27
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#define RRS_PACKET_TYPE_MASK 0x0001
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#define RRS_PACKET_TYPE_SHIFT 28
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#define RRS_FIFO_FULL_MASK 0x0001
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#define RRS_FIFO_FULL_SHIFT 29
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#define RRS_802_3_LEN_ERR_MASK 0x0001
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#define RRS_802_3_LEN_ERR_SHIFT 30
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#define RRS_RXD_UPDATED_MASK 0x0001
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#define RRS_RXD_UPDATED_SHIFT 31
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#define RRS_ERR_L4_CSUM 0x00004000
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#define RRS_ERR_IP_CSUM 0x00008000
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#define RRS_VLAN_INS 0x00010000
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#define RRS_RX_ERR_SUM 0x00100000
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#define RRS_RX_ERR_CRC 0x00200000
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#define RRS_802_3_LEN_ERR 0x40000000
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#define RRS_RXD_UPDATED 0x80000000
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#define RRS_PACKET_TYPE_802_3 1
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#define RRS_PACKET_TYPE_ETH 0
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#define RRS_PACKET_IS_ETH(word) \
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((((word) >> RRS_PACKET_TYPE_SHIFT) & RRS_PACKET_TYPE_MASK) == \
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RRS_PACKET_TYPE_ETH)
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#define RRS_RXD_IS_VALID(word) \
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((((word) >> RRS_RXD_UPDATED_SHIFT) & RRS_RXD_UPDATED_MASK) == 1)
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#define RRS_PACKET_PROT_IS_IPV4_ONLY(word) \
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((((word) >> RRS_PROT_ID_SHIFT) & RRS_PROT_ID_MASK) == 1)
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#define RRS_PACKET_PROT_IS_IPV6_ONLY(word) \
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((((word) >> RRS_PROT_ID_SHIFT) & RRS_PROT_ID_MASK) == 6)
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struct atl1c_recv_ret_status {
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__le32 word0;
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__le32 rss_hash;
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__le16 vlan_tag;
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__le16 flag;
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__le32 word3;
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};
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/* RFD desciptor */
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struct atl1c_rx_free_desc {
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__le64 buffer_addr;
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};
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/* DMA Order Settings */
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enum atl1c_dma_order {
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atl1c_dma_ord_in = 1,
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atl1c_dma_ord_enh = 2,
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atl1c_dma_ord_out = 4
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};
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enum atl1c_dma_rcb {
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atl1c_rcb_64 = 0,
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atl1c_rcb_128 = 1
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};
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enum atl1c_mac_speed {
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atl1c_mac_speed_0 = 0,
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atl1c_mac_speed_10_100 = 1,
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atl1c_mac_speed_1000 = 2
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};
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enum atl1c_dma_req_block {
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atl1c_dma_req_128 = 0,
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atl1c_dma_req_256 = 1,
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atl1c_dma_req_512 = 2,
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atl1c_dma_req_1024 = 3,
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atl1c_dma_req_2048 = 4,
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atl1c_dma_req_4096 = 5
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};
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enum atl1c_rss_mode {
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atl1c_rss_mode_disable = 0,
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atl1c_rss_sig_que = 1,
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atl1c_rss_mul_que_sig_int = 2,
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atl1c_rss_mul_que_mul_int = 4,
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};
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enum atl1c_rss_type {
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atl1c_rss_disable = 0,
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atl1c_rss_ipv4 = 1,
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atl1c_rss_ipv4_tcp = 2,
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atl1c_rss_ipv6 = 4,
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atl1c_rss_ipv6_tcp = 8
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};
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enum atl1c_nic_type {
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athr_l1c = 0,
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athr_l2c = 1,
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athr_l2c_b,
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athr_l2c_b2,
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athr_l1d,
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athr_l1d_2,
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};
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enum atl1c_trans_queue {
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atl1c_trans_normal = 0,
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atl1c_trans_high = 1
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};
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struct atl1c_hw_stats {
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/* rx */
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unsigned long rx_ok; /* The number of good packet received. */
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unsigned long rx_bcast; /* The number of good broadcast packet received. */
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unsigned long rx_mcast; /* The number of good multicast packet received. */
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unsigned long rx_pause; /* The number of Pause packet received. */
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unsigned long rx_ctrl; /* The number of Control packet received other than Pause frame. */
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unsigned long rx_fcs_err; /* The number of packets with bad FCS. */
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unsigned long rx_len_err; /* The number of packets with mismatch of length field and actual size. */
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unsigned long rx_byte_cnt; /* The number of bytes of good packet received. FCS is NOT included. */
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unsigned long rx_runt; /* The number of packets received that are less than 64 byte long and with good FCS. */
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unsigned long rx_frag; /* The number of packets received that are less than 64 byte long and with bad FCS. */
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unsigned long rx_sz_64; /* The number of good and bad packets received that are 64 byte long. */
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unsigned long rx_sz_65_127; /* The number of good and bad packets received that are between 65 and 127-byte long. */
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unsigned long rx_sz_128_255; /* The number of good and bad packets received that are between 128 and 255-byte long. */
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unsigned long rx_sz_256_511; /* The number of good and bad packets received that are between 256 and 511-byte long. */
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unsigned long rx_sz_512_1023; /* The number of good and bad packets received that are between 512 and 1023-byte long. */
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unsigned long rx_sz_1024_1518; /* The number of good and bad packets received that are between 1024 and 1518-byte long. */
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unsigned long rx_sz_1519_max; /* The number of good and bad packets received that are between 1519-byte and MTU. */
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unsigned long rx_sz_ov; /* The number of good and bad packets received that are more than MTU size truncated by Selene. */
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unsigned long rx_rxf_ov; /* The number of frame dropped due to occurrence of RX FIFO overflow. */
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unsigned long rx_rrd_ov; /* The number of frame dropped due to occurrence of RRD overflow. */
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unsigned long rx_align_err; /* Alignment Error */
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unsigned long rx_bcast_byte_cnt; /* The byte count of broadcast packet received, excluding FCS. */
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unsigned long rx_mcast_byte_cnt; /* The byte count of multicast packet received, excluding FCS. */
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unsigned long rx_err_addr; /* The number of packets dropped due to address filtering. */
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/* tx */
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unsigned long tx_ok; /* The number of good packet transmitted. */
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unsigned long tx_bcast; /* The number of good broadcast packet transmitted. */
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unsigned long tx_mcast; /* The number of good multicast packet transmitted. */
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unsigned long tx_pause; /* The number of Pause packet transmitted. */
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unsigned long tx_exc_defer; /* The number of packets transmitted with excessive deferral. */
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unsigned long tx_ctrl; /* The number of packets transmitted is a control frame, excluding Pause frame. */
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unsigned long tx_defer; /* The number of packets transmitted that is deferred. */
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unsigned long tx_byte_cnt; /* The number of bytes of data transmitted. FCS is NOT included. */
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unsigned long tx_sz_64; /* The number of good and bad packets transmitted that are 64 byte long. */
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unsigned long tx_sz_65_127; /* The number of good and bad packets transmitted that are between 65 and 127-byte long. */
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unsigned long tx_sz_128_255; /* The number of good and bad packets transmitted that are between 128 and 255-byte long. */
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unsigned long tx_sz_256_511; /* The number of good and bad packets transmitted that are between 256 and 511-byte long. */
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unsigned long tx_sz_512_1023; /* The number of good and bad packets transmitted that are between 512 and 1023-byte long. */
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unsigned long tx_sz_1024_1518; /* The number of good and bad packets transmitted that are between 1024 and 1518-byte long. */
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unsigned long tx_sz_1519_max; /* The number of good and bad packets transmitted that are between 1519-byte and MTU. */
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unsigned long tx_1_col; /* The number of packets subsequently transmitted successfully with a single prior collision. */
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unsigned long tx_2_col; /* The number of packets subsequently transmitted successfully with multiple prior collisions. */
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unsigned long tx_late_col; /* The number of packets transmitted with late collisions. */
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unsigned long tx_abort_col; /* The number of transmit packets aborted due to excessive collisions. */
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unsigned long tx_underrun; /* The number of transmit packets aborted due to transmit FIFO underrun, or TRD FIFO underrun */
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unsigned long tx_rd_eop; /* The number of times that read beyond the EOP into the next frame area when TRD was not written timely */
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unsigned long tx_len_err; /* The number of transmit packets with length field does NOT match the actual frame size. */
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unsigned long tx_trunc; /* The number of transmit packets truncated due to size exceeding MTU. */
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unsigned long tx_bcast_byte; /* The byte count of broadcast packet transmitted, excluding FCS. */
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unsigned long tx_mcast_byte; /* The byte count of multicast packet transmitted, excluding FCS. */
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};
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struct atl1c_hw {
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u8 __iomem *hw_addr; /* inner register address */
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struct atl1c_adapter *adapter;
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enum atl1c_nic_type nic_type;
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enum atl1c_dma_order dma_order;
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enum atl1c_dma_rcb rcb_value;
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enum atl1c_dma_req_block dmar_block;
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enum atl1c_dma_req_block dmaw_block;
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u16 device_id;
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u16 vendor_id;
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u16 subsystem_id;
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u16 subsystem_vendor_id;
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u8 revision_id;
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u16 phy_id1;
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u16 phy_id2;
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u32 intr_mask;
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u8 dmaw_dly_cnt;
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u8 dmar_dly_cnt;
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u8 preamble_len;
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u16 max_frame_size;
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u16 min_frame_size;
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enum atl1c_mac_speed mac_speed;
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bool mac_duplex;
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bool hibernate;
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u16 media_type;
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#define MEDIA_TYPE_AUTO_SENSOR 0
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#define MEDIA_TYPE_100M_FULL 1
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#define MEDIA_TYPE_100M_HALF 2
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#define MEDIA_TYPE_10M_FULL 3
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#define MEDIA_TYPE_10M_HALF 4
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u16 autoneg_advertised;
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u16 mii_autoneg_adv_reg;
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u16 mii_1000t_ctrl_reg;
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u16 tx_imt; /* TX Interrupt Moderator timer ( 2us resolution) */
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u16 rx_imt; /* RX Interrupt Moderator timer ( 2us resolution) */
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u16 ict; /* Interrupt Clear timer (2us resolution) */
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u16 ctrl_flags;
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#define ATL1C_INTR_CLEAR_ON_READ 0x0001
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#define ATL1C_INTR_MODRT_ENABLE 0x0002
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#define ATL1C_CMB_ENABLE 0x0004
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#define ATL1C_SMB_ENABLE 0x0010
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#define ATL1C_TXQ_MODE_ENHANCE 0x0020
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#define ATL1C_RX_IPV6_CHKSUM 0x0040
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#define ATL1C_ASPM_L0S_SUPPORT 0x0080
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#define ATL1C_ASPM_L1_SUPPORT 0x0100
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#define ATL1C_ASPM_CTRL_MON 0x0200
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#define ATL1C_HIB_DISABLE 0x0400
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#define ATL1C_APS_MODE_ENABLE 0x0800
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#define ATL1C_LINK_EXT_SYNC 0x1000
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#define ATL1C_CLK_GATING_EN 0x2000
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#define ATL1C_FPGA_VERSION 0x8000
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u16 link_cap_flags;
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#define ATL1C_LINK_CAP_1000M 0x0001
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u16 cmb_tpd;
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u16 cmb_rrd;
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u16 cmb_rx_timer; /* 2us resolution */
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u16 cmb_tx_timer;
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u32 smb_timer;
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u16 rrd_thresh; /* Threshold of number of RRD produced to trigger
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interrupt request */
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u16 tpd_thresh;
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u8 tpd_burst; /* Number of TPD to prefetch in cache-aligned burst. */
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u8 rfd_burst;
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enum atl1c_rss_type rss_type;
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enum atl1c_rss_mode rss_mode;
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u8 rss_hash_bits;
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u32 base_cpu;
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u32 indirect_tab;
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u8 mac_addr[ETH_ALEN];
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u8 perm_mac_addr[ETH_ALEN];
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bool phy_configured;
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bool re_autoneg;
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bool emi_ca;
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};
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/*
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* atl1c_ring_header represents a single, contiguous block of DMA space
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* mapped for the three descriptor rings (tpd, rfd, rrd) and the two
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* message blocks (cmb, smb) described below
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*/
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struct atl1c_ring_header {
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void *desc; /* virtual address */
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dma_addr_t dma; /* physical address*/
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unsigned int size; /* length in bytes */
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};
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/*
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* atl1c_buffer is wrapper around a pointer to a socket buffer
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* so a DMA handle can be stored along with the skb
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*/
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struct atl1c_buffer {
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struct sk_buff *skb; /* socket buffer */
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u16 length; /* rx buffer length */
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u16 flags; /* information of buffer */
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#define ATL1C_BUFFER_FREE 0x0001
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#define ATL1C_BUFFER_BUSY 0x0002
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#define ATL1C_BUFFER_STATE_MASK 0x0003
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#define ATL1C_PCIMAP_SINGLE 0x0004
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#define ATL1C_PCIMAP_PAGE 0x0008
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#define ATL1C_PCIMAP_TYPE_MASK 0x000C
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#define ATL1C_PCIMAP_TODEVICE 0x0010
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#define ATL1C_PCIMAP_FROMDEVICE 0x0020
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#define ATL1C_PCIMAP_DIRECTION_MASK 0x0030
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dma_addr_t dma;
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};
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#define ATL1C_SET_BUFFER_STATE(buff, state) do { \
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((buff)->flags) &= ~ATL1C_BUFFER_STATE_MASK; \
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((buff)->flags) |= (state); \
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} while (0)
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#define ATL1C_SET_PCIMAP_TYPE(buff, type, direction) do { \
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((buff)->flags) &= ~ATL1C_PCIMAP_TYPE_MASK; \
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((buff)->flags) |= (type); \
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((buff)->flags) &= ~ATL1C_PCIMAP_DIRECTION_MASK; \
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((buff)->flags) |= (direction); \
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} while (0)
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/* transimit packet descriptor (tpd) ring */
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struct atl1c_tpd_ring {
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void *desc; /* descriptor ring virtual address */
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dma_addr_t dma; /* descriptor ring physical address */
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u16 size; /* descriptor ring length in bytes */
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u16 count; /* number of descriptors in the ring */
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u16 next_to_use; /* this is protectd by adapter->tx_lock */
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atomic_t next_to_clean;
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struct atl1c_buffer *buffer_info;
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};
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/* receive free descriptor (rfd) ring */
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struct atl1c_rfd_ring {
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void *desc; /* descriptor ring virtual address */
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dma_addr_t dma; /* descriptor ring physical address */
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u16 size; /* descriptor ring length in bytes */
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u16 count; /* number of descriptors in the ring */
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u16 next_to_use;
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u16 next_to_clean;
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struct atl1c_buffer *buffer_info;
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};
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/* receive return desciptor (rrd) ring */
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struct atl1c_rrd_ring {
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void *desc; /* descriptor ring virtual address */
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dma_addr_t dma; /* descriptor ring physical address */
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u16 size; /* descriptor ring length in bytes */
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u16 count; /* number of descriptors in the ring */
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u16 next_to_use;
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u16 next_to_clean;
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};
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struct atl1c_cmb {
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void *cmb;
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dma_addr_t dma;
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};
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struct atl1c_smb {
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void *smb;
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dma_addr_t dma;
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};
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/* board specific private data structure */
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struct atl1c_adapter {
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struct net_device *netdev;
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struct pci_dev *pdev;
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struct vlan_group *vlgrp;
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struct napi_struct napi;
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struct atl1c_hw hw;
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struct atl1c_hw_stats hw_stats;
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struct net_device_stats net_stats;
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struct mii_if_info mii; /* MII interface info */
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u16 rx_buffer_len;
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unsigned long flags;
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#define __AT_TESTING 0x0001
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#define __AT_RESETTING 0x0002
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#define __AT_DOWN 0x0003
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u8 work_event;
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#define ATL1C_WORK_EVENT_RESET 0x01
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#define ATL1C_WORK_EVENT_LINK_CHANGE 0x02
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u32 msg_enable;
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bool have_msi;
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u32 wol;
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u16 link_speed;
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u16 link_duplex;
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spinlock_t mdio_lock;
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spinlock_t tx_lock;
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atomic_t irq_sem;
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struct work_struct common_task;
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struct timer_list watchdog_timer;
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struct timer_list phy_config_timer;
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/* All Descriptor memory */
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struct atl1c_ring_header ring_header;
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struct atl1c_tpd_ring tpd_ring[AT_MAX_TRANSMIT_QUEUE];
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struct atl1c_rfd_ring rfd_ring[AT_MAX_RECEIVE_QUEUE];
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struct atl1c_rrd_ring rrd_ring[AT_MAX_RECEIVE_QUEUE];
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struct atl1c_cmb cmb;
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struct atl1c_smb smb;
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int num_rx_queues;
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u32 bd_number; /* board number;*/
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};
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#define AT_WRITE_REG(a, reg, value) ( \
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writel((value), ((a)->hw_addr + reg)))
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#define AT_WRITE_FLUSH(a) (\
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readl((a)->hw_addr))
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#define AT_READ_REG(a, reg, pdata) do { \
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if (unlikely((a)->hibernate)) { \
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readl((a)->hw_addr + reg); \
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*(u32 *)pdata = readl((a)->hw_addr + reg); \
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} else { \
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*(u32 *)pdata = readl((a)->hw_addr + reg); \
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} \
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} while (0)
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#define AT_WRITE_REGB(a, reg, value) (\
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writeb((value), ((a)->hw_addr + reg)))
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#define AT_READ_REGB(a, reg) (\
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readb((a)->hw_addr + reg))
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#define AT_WRITE_REGW(a, reg, value) (\
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writew((value), ((a)->hw_addr + reg)))
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#define AT_READ_REGW(a, reg) (\
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readw((a)->hw_addr + reg))
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#define AT_WRITE_REG_ARRAY(a, reg, offset, value) ( \
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writel((value), (((a)->hw_addr + reg) + ((offset) << 2))))
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#define AT_READ_REG_ARRAY(a, reg, offset) ( \
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readl(((a)->hw_addr + reg) + ((offset) << 2)))
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extern char atl1c_driver_name[];
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extern char atl1c_driver_version[];
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extern int atl1c_up(struct atl1c_adapter *adapter);
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extern void atl1c_down(struct atl1c_adapter *adapter);
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extern void atl1c_reinit_locked(struct atl1c_adapter *adapter);
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extern s32 atl1c_reset_hw(struct atl1c_hw *hw);
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extern void atl1c_set_ethtool_ops(struct net_device *netdev);
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#endif /* _ATL1C_H_ */
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