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d2b194ed82
The math emulation code is centered around a set of generic macros that provide the core of the emulation that are shared by the various architectures and other projects (like glibc). Each arch implements its own sfp-machine.h to specific various arch specific details. For historic reasons that are now lost the powerpc math-emu code had its own version of the common headers. This moves us to using the kernel generic version and thus getting fixes when those are updated. Also cleaned up exception/error reporting from the FP emulation functions. Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
490 lines
12 KiB
C
490 lines
12 KiB
C
/*
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* Copyright (C) 1999 Eddie C. Dost (ecd@atecom.com)
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*/
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#include <linux/types.h>
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#include <linux/sched.h>
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#include <asm/uaccess.h>
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#include <asm/reg.h>
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#include <asm/sfp-machine.h>
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#include <math-emu/double.h>
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#define FLOATFUNC(x) extern int x(void *, void *, void *, void *)
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FLOATFUNC(fadd);
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FLOATFUNC(fadds);
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FLOATFUNC(fdiv);
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FLOATFUNC(fdivs);
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FLOATFUNC(fmul);
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FLOATFUNC(fmuls);
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FLOATFUNC(fsub);
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FLOATFUNC(fsubs);
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FLOATFUNC(fmadd);
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FLOATFUNC(fmadds);
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FLOATFUNC(fmsub);
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FLOATFUNC(fmsubs);
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FLOATFUNC(fnmadd);
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FLOATFUNC(fnmadds);
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FLOATFUNC(fnmsub);
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FLOATFUNC(fnmsubs);
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FLOATFUNC(fctiw);
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FLOATFUNC(fctiwz);
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FLOATFUNC(frsp);
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FLOATFUNC(fcmpo);
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FLOATFUNC(fcmpu);
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FLOATFUNC(mcrfs);
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FLOATFUNC(mffs);
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FLOATFUNC(mtfsb0);
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FLOATFUNC(mtfsb1);
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FLOATFUNC(mtfsf);
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FLOATFUNC(mtfsfi);
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FLOATFUNC(lfd);
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FLOATFUNC(lfs);
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FLOATFUNC(stfd);
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FLOATFUNC(stfs);
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FLOATFUNC(stfiwx);
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FLOATFUNC(fabs);
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FLOATFUNC(fmr);
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FLOATFUNC(fnabs);
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FLOATFUNC(fneg);
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/* Optional */
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FLOATFUNC(fres);
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FLOATFUNC(frsqrte);
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FLOATFUNC(fsel);
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FLOATFUNC(fsqrt);
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FLOATFUNC(fsqrts);
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#define OP31 0x1f /* 31 */
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#define LFS 0x30 /* 48 */
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#define LFSU 0x31 /* 49 */
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#define LFD 0x32 /* 50 */
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#define LFDU 0x33 /* 51 */
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#define STFS 0x34 /* 52 */
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#define STFSU 0x35 /* 53 */
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#define STFD 0x36 /* 54 */
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#define STFDU 0x37 /* 55 */
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#define OP59 0x3b /* 59 */
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#define OP63 0x3f /* 63 */
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/* Opcode 31: */
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/* X-Form: */
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#define LFSX 0x217 /* 535 */
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#define LFSUX 0x237 /* 567 */
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#define LFDX 0x257 /* 599 */
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#define LFDUX 0x277 /* 631 */
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#define STFSX 0x297 /* 663 */
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#define STFSUX 0x2b7 /* 695 */
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#define STFDX 0x2d7 /* 727 */
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#define STFDUX 0x2f7 /* 759 */
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#define STFIWX 0x3d7 /* 983 */
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/* Opcode 59: */
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/* A-Form: */
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#define FDIVS 0x012 /* 18 */
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#define FSUBS 0x014 /* 20 */
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#define FADDS 0x015 /* 21 */
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#define FSQRTS 0x016 /* 22 */
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#define FRES 0x018 /* 24 */
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#define FMULS 0x019 /* 25 */
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#define FMSUBS 0x01c /* 28 */
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#define FMADDS 0x01d /* 29 */
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#define FNMSUBS 0x01e /* 30 */
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#define FNMADDS 0x01f /* 31 */
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/* Opcode 63: */
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/* A-Form: */
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#define FDIV 0x012 /* 18 */
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#define FSUB 0x014 /* 20 */
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#define FADD 0x015 /* 21 */
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#define FSQRT 0x016 /* 22 */
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#define FSEL 0x017 /* 23 */
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#define FMUL 0x019 /* 25 */
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#define FRSQRTE 0x01a /* 26 */
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#define FMSUB 0x01c /* 28 */
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#define FMADD 0x01d /* 29 */
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#define FNMSUB 0x01e /* 30 */
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#define FNMADD 0x01f /* 31 */
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/* X-Form: */
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#define FCMPU 0x000 /* 0 */
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#define FRSP 0x00c /* 12 */
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#define FCTIW 0x00e /* 14 */
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#define FCTIWZ 0x00f /* 15 */
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#define FCMPO 0x020 /* 32 */
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#define MTFSB1 0x026 /* 38 */
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#define FNEG 0x028 /* 40 */
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#define MCRFS 0x040 /* 64 */
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#define MTFSB0 0x046 /* 70 */
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#define FMR 0x048 /* 72 */
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#define MTFSFI 0x086 /* 134 */
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#define FNABS 0x088 /* 136 */
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#define FABS 0x108 /* 264 */
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#define MFFS 0x247 /* 583 */
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#define MTFSF 0x2c7 /* 711 */
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#define AB 2
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#define AC 3
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#define ABC 4
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#define D 5
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#define DU 6
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#define X 7
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#define XA 8
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#define XB 9
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#define XCR 11
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#define XCRB 12
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#define XCRI 13
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#define XCRL 16
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#define XE 14
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#define XEU 15
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#define XFLB 10
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#ifdef CONFIG_MATH_EMULATION
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static int
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record_exception(struct pt_regs *regs, int eflag)
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{
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u32 fpscr;
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fpscr = __FPU_FPSCR;
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if (eflag) {
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fpscr |= FPSCR_FX;
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if (eflag & EFLAG_OVERFLOW)
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fpscr |= FPSCR_OX;
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if (eflag & EFLAG_UNDERFLOW)
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fpscr |= FPSCR_UX;
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if (eflag & EFLAG_DIVZERO)
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fpscr |= FPSCR_ZX;
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if (eflag & EFLAG_INEXACT)
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fpscr |= FPSCR_XX;
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if (eflag & EFLAG_INVALID)
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fpscr |= FPSCR_VX;
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if (eflag & EFLAG_VXSNAN)
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fpscr |= FPSCR_VXSNAN;
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if (eflag & EFLAG_VXISI)
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fpscr |= FPSCR_VXISI;
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if (eflag & EFLAG_VXIDI)
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fpscr |= FPSCR_VXIDI;
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if (eflag & EFLAG_VXZDZ)
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fpscr |= FPSCR_VXZDZ;
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if (eflag & EFLAG_VXIMZ)
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fpscr |= FPSCR_VXIMZ;
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if (eflag & EFLAG_VXVC)
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fpscr |= FPSCR_VXVC;
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if (eflag & EFLAG_VXSOFT)
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fpscr |= FPSCR_VXSOFT;
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if (eflag & EFLAG_VXSQRT)
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fpscr |= FPSCR_VXSQRT;
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if (eflag & EFLAG_VXCVI)
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fpscr |= FPSCR_VXCVI;
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}
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// fpscr &= ~(FPSCR_VX);
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if (fpscr & (FPSCR_VXSNAN | FPSCR_VXISI | FPSCR_VXIDI |
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FPSCR_VXZDZ | FPSCR_VXIMZ | FPSCR_VXVC |
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FPSCR_VXSOFT | FPSCR_VXSQRT | FPSCR_VXCVI))
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fpscr |= FPSCR_VX;
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fpscr &= ~(FPSCR_FEX);
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if (((fpscr & FPSCR_VX) && (fpscr & FPSCR_VE)) ||
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((fpscr & FPSCR_OX) && (fpscr & FPSCR_OE)) ||
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((fpscr & FPSCR_UX) && (fpscr & FPSCR_UE)) ||
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((fpscr & FPSCR_ZX) && (fpscr & FPSCR_ZE)) ||
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((fpscr & FPSCR_XX) && (fpscr & FPSCR_XE)))
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fpscr |= FPSCR_FEX;
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__FPU_FPSCR = fpscr;
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return (fpscr & FPSCR_FEX) ? 1 : 0;
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}
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#endif /* CONFIG_MATH_EMULATION */
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int
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do_mathemu(struct pt_regs *regs)
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{
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void *op0 = 0, *op1 = 0, *op2 = 0, *op3 = 0;
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unsigned long pc = regs->nip;
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signed short sdisp;
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u32 insn = 0;
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int idx = 0;
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#ifdef CONFIG_MATH_EMULATION
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int (*func)(void *, void *, void *, void *);
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int type = 0;
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int eflag, trap;
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#endif
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if (get_user(insn, (u32 *)pc))
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return -EFAULT;
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#ifndef CONFIG_MATH_EMULATION
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switch (insn >> 26) {
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case LFD:
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idx = (insn >> 16) & 0x1f;
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sdisp = (insn & 0xffff);
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op0 = (void *)¤t->thread.TS_FPR((insn >> 21) & 0x1f);
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op1 = (void *)((idx ? regs->gpr[idx] : 0) + sdisp);
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lfd(op0, op1, op2, op3);
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break;
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case LFDU:
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idx = (insn >> 16) & 0x1f;
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sdisp = (insn & 0xffff);
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op0 = (void *)¤t->thread.TS_FPR((insn >> 21) & 0x1f);
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op1 = (void *)((idx ? regs->gpr[idx] : 0) + sdisp);
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lfd(op0, op1, op2, op3);
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regs->gpr[idx] = (unsigned long)op1;
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break;
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case STFD:
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idx = (insn >> 16) & 0x1f;
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sdisp = (insn & 0xffff);
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op0 = (void *)¤t->thread.TS_FPR((insn >> 21) & 0x1f);
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op1 = (void *)((idx ? regs->gpr[idx] : 0) + sdisp);
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stfd(op0, op1, op2, op3);
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break;
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case STFDU:
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idx = (insn >> 16) & 0x1f;
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sdisp = (insn & 0xffff);
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op0 = (void *)¤t->thread.TS_FPR((insn >> 21) & 0x1f);
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op1 = (void *)((idx ? regs->gpr[idx] : 0) + sdisp);
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stfd(op0, op1, op2, op3);
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regs->gpr[idx] = (unsigned long)op1;
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break;
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case OP63:
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op0 = (void *)¤t->thread.TS_FPR((insn >> 21) & 0x1f);
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op1 = (void *)¤t->thread.TS_FPR((insn >> 11) & 0x1f);
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fmr(op0, op1, op2, op3);
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break;
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default:
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goto illegal;
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}
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#else /* CONFIG_MATH_EMULATION */
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switch (insn >> 26) {
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case LFS: func = lfs; type = D; break;
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case LFSU: func = lfs; type = DU; break;
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case LFD: func = lfd; type = D; break;
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case LFDU: func = lfd; type = DU; break;
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case STFS: func = stfs; type = D; break;
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case STFSU: func = stfs; type = DU; break;
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case STFD: func = stfd; type = D; break;
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case STFDU: func = stfd; type = DU; break;
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case OP31:
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switch ((insn >> 1) & 0x3ff) {
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case LFSX: func = lfs; type = XE; break;
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case LFSUX: func = lfs; type = XEU; break;
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case LFDX: func = lfd; type = XE; break;
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case LFDUX: func = lfd; type = XEU; break;
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case STFSX: func = stfs; type = XE; break;
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case STFSUX: func = stfs; type = XEU; break;
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case STFDX: func = stfd; type = XE; break;
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case STFDUX: func = stfd; type = XEU; break;
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case STFIWX: func = stfiwx; type = XE; break;
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default:
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goto illegal;
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}
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break;
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case OP59:
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switch ((insn >> 1) & 0x1f) {
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case FDIVS: func = fdivs; type = AB; break;
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case FSUBS: func = fsubs; type = AB; break;
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case FADDS: func = fadds; type = AB; break;
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case FSQRTS: func = fsqrts; type = AB; break;
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case FRES: func = fres; type = AB; break;
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case FMULS: func = fmuls; type = AC; break;
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case FMSUBS: func = fmsubs; type = ABC; break;
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case FMADDS: func = fmadds; type = ABC; break;
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case FNMSUBS: func = fnmsubs; type = ABC; break;
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case FNMADDS: func = fnmadds; type = ABC; break;
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default:
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goto illegal;
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}
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break;
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case OP63:
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if (insn & 0x20) {
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switch ((insn >> 1) & 0x1f) {
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case FDIV: func = fdiv; type = AB; break;
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case FSUB: func = fsub; type = AB; break;
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case FADD: func = fadd; type = AB; break;
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case FSQRT: func = fsqrt; type = AB; break;
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case FSEL: func = fsel; type = ABC; break;
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case FMUL: func = fmul; type = AC; break;
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case FRSQRTE: func = frsqrte; type = AB; break;
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case FMSUB: func = fmsub; type = ABC; break;
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case FMADD: func = fmadd; type = ABC; break;
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case FNMSUB: func = fnmsub; type = ABC; break;
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case FNMADD: func = fnmadd; type = ABC; break;
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default:
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goto illegal;
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}
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break;
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}
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switch ((insn >> 1) & 0x3ff) {
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case FCMPU: func = fcmpu; type = XCR; break;
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case FRSP: func = frsp; type = XB; break;
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case FCTIW: func = fctiw; type = XB; break;
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case FCTIWZ: func = fctiwz; type = XB; break;
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case FCMPO: func = fcmpo; type = XCR; break;
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case MTFSB1: func = mtfsb1; type = XCRB; break;
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case FNEG: func = fneg; type = XB; break;
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case MCRFS: func = mcrfs; type = XCRL; break;
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case MTFSB0: func = mtfsb0; type = XCRB; break;
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case FMR: func = fmr; type = XB; break;
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case MTFSFI: func = mtfsfi; type = XCRI; break;
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case FNABS: func = fnabs; type = XB; break;
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case FABS: func = fabs; type = XB; break;
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case MFFS: func = mffs; type = X; break;
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case MTFSF: func = mtfsf; type = XFLB; break;
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default:
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goto illegal;
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}
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break;
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default:
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goto illegal;
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}
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switch (type) {
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case AB:
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op0 = (void *)¤t->thread.TS_FPR((insn >> 21) & 0x1f);
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op1 = (void *)¤t->thread.TS_FPR((insn >> 16) & 0x1f);
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op2 = (void *)¤t->thread.TS_FPR((insn >> 11) & 0x1f);
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break;
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case AC:
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op0 = (void *)¤t->thread.TS_FPR((insn >> 21) & 0x1f);
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op1 = (void *)¤t->thread.TS_FPR((insn >> 16) & 0x1f);
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op2 = (void *)¤t->thread.TS_FPR((insn >> 6) & 0x1f);
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break;
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case ABC:
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op0 = (void *)¤t->thread.TS_FPR((insn >> 21) & 0x1f);
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op1 = (void *)¤t->thread.TS_FPR((insn >> 16) & 0x1f);
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op2 = (void *)¤t->thread.TS_FPR((insn >> 11) & 0x1f);
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op3 = (void *)¤t->thread.TS_FPR((insn >> 6) & 0x1f);
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break;
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case D:
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idx = (insn >> 16) & 0x1f;
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sdisp = (insn & 0xffff);
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op0 = (void *)¤t->thread.TS_FPR((insn >> 21) & 0x1f);
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op1 = (void *)((idx ? regs->gpr[idx] : 0) + sdisp);
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break;
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case DU:
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idx = (insn >> 16) & 0x1f;
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if (!idx)
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goto illegal;
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sdisp = (insn & 0xffff);
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op0 = (void *)¤t->thread.TS_FPR((insn >> 21) & 0x1f);
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op1 = (void *)(regs->gpr[idx] + sdisp);
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break;
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case X:
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op0 = (void *)¤t->thread.TS_FPR((insn >> 21) & 0x1f);
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break;
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case XA:
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op0 = (void *)¤t->thread.TS_FPR((insn >> 21) & 0x1f);
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op1 = (void *)¤t->thread.TS_FPR((insn >> 16) & 0x1f);
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break;
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case XB:
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op0 = (void *)¤t->thread.TS_FPR((insn >> 21) & 0x1f);
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op1 = (void *)¤t->thread.TS_FPR((insn >> 11) & 0x1f);
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break;
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case XE:
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idx = (insn >> 16) & 0x1f;
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op0 = (void *)¤t->thread.TS_FPR((insn >> 21) & 0x1f);
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if (!idx) {
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if (((insn >> 1) & 0x3ff) == STFIWX)
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op1 = (void *)(regs->gpr[(insn >> 11) & 0x1f]);
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else
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goto illegal;
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} else {
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op1 = (void *)(regs->gpr[idx] + regs->gpr[(insn >> 11) & 0x1f]);
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}
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break;
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case XEU:
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idx = (insn >> 16) & 0x1f;
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op0 = (void *)¤t->thread.TS_FPR((insn >> 21) & 0x1f);
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op1 = (void *)((idx ? regs->gpr[idx] : 0)
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+ regs->gpr[(insn >> 11) & 0x1f]);
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break;
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case XCR:
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op0 = (void *)®s->ccr;
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op1 = (void *)((insn >> 23) & 0x7);
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op2 = (void *)¤t->thread.TS_FPR((insn >> 16) & 0x1f);
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op3 = (void *)¤t->thread.TS_FPR((insn >> 11) & 0x1f);
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break;
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case XCRL:
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op0 = (void *)®s->ccr;
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op1 = (void *)((insn >> 23) & 0x7);
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op2 = (void *)((insn >> 18) & 0x7);
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break;
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case XCRB:
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op0 = (void *)((insn >> 21) & 0x1f);
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break;
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|
|
|
case XCRI:
|
|
op0 = (void *)((insn >> 23) & 0x7);
|
|
op1 = (void *)((insn >> 12) & 0xf);
|
|
break;
|
|
|
|
case XFLB:
|
|
op0 = (void *)((insn >> 17) & 0xff);
|
|
op1 = (void *)¤t->thread.TS_FPR((insn >> 11) & 0x1f);
|
|
break;
|
|
|
|
default:
|
|
goto illegal;
|
|
}
|
|
|
|
eflag = func(op0, op1, op2, op3);
|
|
|
|
if (insn & 1) {
|
|
regs->ccr &= ~(0x0f000000);
|
|
regs->ccr |= (__FPU_FPSCR >> 4) & 0x0f000000;
|
|
}
|
|
|
|
trap = record_exception(regs, eflag);
|
|
if (trap)
|
|
return 1;
|
|
|
|
switch (type) {
|
|
case DU:
|
|
case XEU:
|
|
regs->gpr[idx] = (unsigned long)op1;
|
|
break;
|
|
|
|
default:
|
|
break;
|
|
}
|
|
#endif /* CONFIG_MATH_EMULATION */
|
|
|
|
regs->nip += 4;
|
|
return 0;
|
|
|
|
illegal:
|
|
return -ENOSYS;
|
|
}
|