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Some GDSCs might support a HW control mode, where in the power domain (gdsc) is brought in and out of low power state (while unsued) without any SW assistance, saving power. Such GDSCs can be configured in a HW control mode when powered on until they are explicitly requested to be powered off by software. Signed-off-by: Rajendra Nayak <rnayak@codeaurora.org> Signed-off-by: Sricharan R <sricharan@codeaurora.org> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
82 lines
2.3 KiB
C
82 lines
2.3 KiB
C
/*
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* Copyright (c) 2015, The Linux Foundation. All rights reserved.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 and
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* only version 2 as published by the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#ifndef __QCOM_GDSC_H__
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#define __QCOM_GDSC_H__
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#include <linux/err.h>
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#include <linux/pm_domain.h>
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struct regmap;
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struct reset_controller_dev;
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/**
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* struct gdsc - Globally Distributed Switch Controller
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* @pd: generic power domain
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* @regmap: regmap for MMIO accesses
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* @gdscr: gsdc control register
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* @gds_hw_ctrl: gds_hw_ctrl register
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* @cxcs: offsets of branch registers to toggle mem/periph bits in
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* @cxc_count: number of @cxcs
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* @pwrsts: Possible powerdomain power states
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* @resets: ids of resets associated with this gdsc
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* @reset_count: number of @resets
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* @rcdev: reset controller
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*/
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struct gdsc {
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struct generic_pm_domain pd;
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struct generic_pm_domain *parent;
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struct regmap *regmap;
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unsigned int gdscr;
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unsigned int gds_hw_ctrl;
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unsigned int clamp_io_ctrl;
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unsigned int *cxcs;
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unsigned int cxc_count;
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const u8 pwrsts;
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/* Powerdomain allowable state bitfields */
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#define PWRSTS_OFF BIT(0)
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#define PWRSTS_RET BIT(1)
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#define PWRSTS_ON BIT(2)
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#define PWRSTS_OFF_ON (PWRSTS_OFF | PWRSTS_ON)
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#define PWRSTS_RET_ON (PWRSTS_RET | PWRSTS_ON)
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const u8 flags;
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#define VOTABLE BIT(0)
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#define CLAMP_IO BIT(1)
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#define HW_CTRL BIT(2)
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struct reset_controller_dev *rcdev;
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unsigned int *resets;
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unsigned int reset_count;
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};
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struct gdsc_desc {
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struct device *dev;
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struct gdsc **scs;
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size_t num;
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};
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#ifdef CONFIG_QCOM_GDSC
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int gdsc_register(struct gdsc_desc *desc, struct reset_controller_dev *,
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struct regmap *);
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void gdsc_unregister(struct gdsc_desc *desc);
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#else
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static inline int gdsc_register(struct gdsc_desc *desc,
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struct reset_controller_dev *rcdev,
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struct regmap *r)
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{
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return -ENOSYS;
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}
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static inline void gdsc_unregister(struct gdsc_desc *desc) {};
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#endif /* CONFIG_QCOM_GDSC */
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#endif /* __QCOM_GDSC_H__ */
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