Nicholas Piggin 3437d3c886 nios2: Use an invalid TLB entry address helper function ... There is no need for complicated calculation for an invalid address that maps to the same TLB index as the entry to be invalidated. Using the TLB address plus the two top bits set puts the address into the kernel TLB bypass range and still maps to the same cache line. This is also a bug fix for flush_tlb_pid, which is currently unused, but does not set PTEADDR to invalid. Signed-off-by: Nicholas Piggin <npiggin@gmail.com> Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com>		2019-03-07 05:29:35 +08:00
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cacheflush.c	nios2: update_mmu_cache clear the old entry from the TLB	2019-03-07 05:29:35 +08:00
dma-mapping.c	nios2: use generic dma_noncoherent_ops	2018-07-25 13:33:09 +02:00
extable.c	nios2: migrate exception table users off module.h and onto extable.h	2017-01-26 10:58:14 -05:00
fault.c	nios2: flush_tlb_page use PID based flush	2019-03-07 05:29:35 +08:00
init.c	mm: remove include/linux/bootmem.h	2018-10-31 08:54:16 -07:00
ioremap.c
Makefile	License cleanup: add SPDX GPL-2.0 license identifier to files with no license	2017-11-02 11:10:55 +01:00
mmu_context.c	nios2: Process management	2014-12-08 12:55:53 +08:00
pgtable.c	nios2: Page table management	2014-12-08 12:55:53 +08:00
tlb.c	nios2: Use an invalid TLB entry address helper function	2019-03-07 05:29:35 +08:00
uaccess.c	nios2: use generic strncpy_from_user() and strnlen_user()	2017-05-08 17:14:14 +08:00