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652b56b184
Switch to the batched version of the jump label update functions so instruction cache maintenance is deferred until the end of the update. Reviewed-by: Björn Töpel <bjorn@rivosinc.com> Signed-off-by: Samuel Holland <samuel.holland@sifive.com> Link: https://lore.kernel.org/r/20240327160520.791322-2-samuel.holland@sifive.com Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>
50 lines
1.2 KiB
C
50 lines
1.2 KiB
C
// SPDX-License-Identifier: GPL-2.0-only
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/*
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* Copyright (C) 2020 Emil Renner Berthing
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*
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* Based on arch/arm64/kernel/jump_label.c
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*/
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#include <linux/jump_label.h>
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#include <linux/kernel.h>
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#include <linux/memory.h>
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#include <linux/mutex.h>
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#include <asm/bug.h>
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#include <asm/cacheflush.h>
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#include <asm/patch.h>
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#define RISCV_INSN_NOP 0x00000013U
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#define RISCV_INSN_JAL 0x0000006fU
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bool arch_jump_label_transform_queue(struct jump_entry *entry,
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enum jump_label_type type)
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{
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void *addr = (void *)jump_entry_code(entry);
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u32 insn;
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if (type == JUMP_LABEL_JMP) {
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long offset = jump_entry_target(entry) - jump_entry_code(entry);
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if (WARN_ON(offset & 1 || offset < -524288 || offset >= 524288))
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return true;
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insn = RISCV_INSN_JAL |
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(((u32)offset & GENMASK(19, 12)) << (12 - 12)) |
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(((u32)offset & GENMASK(11, 11)) << (20 - 11)) |
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(((u32)offset & GENMASK(10, 1)) << (21 - 1)) |
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(((u32)offset & GENMASK(20, 20)) << (31 - 20));
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} else {
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insn = RISCV_INSN_NOP;
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}
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mutex_lock(&text_mutex);
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patch_insn_write(addr, &insn, sizeof(insn));
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mutex_unlock(&text_mutex);
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return true;
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}
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void arch_jump_label_transform_apply(void)
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{
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flush_icache_all();
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}
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