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USIv2 IP-core is found on modern ARM64 Exynos SoCs (like Exynos850) and
provides selectable serial protocol (one of: UART, SPI, I2C). USIv2
registers usually reside in the same register map as a particular
underlying protocol it implements, but have some particular offset. E.g.
on Exynos850 the USI_UART has 0x13820000 base address, where UART
registers have 0x00..0x40 offsets, and USI registers have 0xc0..0xdc
offsets. Desired protocol can be chosen via SW_CONF register from System
Register block of the same domain as USI.
Before starting to use a particular protocol, USIv2 must be configured
properly:
1. Select protocol to be used via System Register
2. Clear "reset" flag in USI_CON
3. Configure HWACG behavior (e.g. for UART Rx the HWACG must be
disabled, so that the IP clock is not gated automatically); this is
done using USI_OPTION register
4. Keep both USI clocks (PCLK and IPCLK) running during USI registers
modification
This driver implements the above behavior. Of course, USIv2 driver
should be probed before UART/I2C/SPI drivers. It can be achieved by
embedding UART/I2C/SPI nodes inside of the USI node (in Device Tree);
driver then walks underlying nodes and instantiates those. Driver also
handles USI configuration on PM resume, as register contents can be lost
during CPU suspend.
This driver is designed with different USI versions in mind. So it
should be relatively easy to add new USI revisions to it later.
Signed-off-by: Sam Protsenko <semen.protsenko@linaro.org>
Link: https://lore.kernel.org/r/20211204195757.8600-3-semen.protsenko@linaro.org
Tested-by: Chanho Park <chanho61.park@samsung.com>
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@canonical.com>
106 lines
3.5 KiB
Plaintext
106 lines
3.5 KiB
Plaintext
# SPDX-License-Identifier: GPL-2.0
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#
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# Samsung SoC drivers
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#
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menuconfig SOC_SAMSUNG
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bool "Samsung SoC driver support" if COMPILE_TEST
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if SOC_SAMSUNG
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# There is no need to enable these drivers for ARMv8
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config EXYNOS_ASV_ARM
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bool "Exynos ASV ARMv7-specific driver extensions" if COMPILE_TEST
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depends on EXYNOS_CHIPID
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config EXYNOS_CHIPID
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tristate "Exynos ChipID controller and ASV driver"
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depends on ARCH_EXYNOS || COMPILE_TEST
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default ARCH_EXYNOS
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select EXYNOS_ASV_ARM if ARM && ARCH_EXYNOS
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select MFD_SYSCON
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select SOC_BUS
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help
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Support for Samsung Exynos SoC ChipID and Adaptive Supply Voltage.
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This driver can also be built as module (exynos_chipid).
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config EXYNOS_USI
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tristate "Exynos USI (Universal Serial Interface) driver"
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default ARCH_EXYNOS && ARM64
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depends on ARCH_EXYNOS || COMPILE_TEST
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select MFD_SYSCON
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help
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Enable support for USI block. USI (Universal Serial Interface) is an
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IP-core found in modern Samsung Exynos SoCs, like Exynos850 and
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ExynosAutoV0. USI block can be configured to provide one of the
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following serial protocols: UART, SPI or High Speed I2C.
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This driver allows one to configure USI for desired protocol, which
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is usually done in USI node in Device Tree.
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config EXYNOS_PMU
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bool "Exynos PMU controller driver" if COMPILE_TEST
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depends on ARCH_EXYNOS || ((ARM || ARM64) && COMPILE_TEST)
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select EXYNOS_PMU_ARM_DRIVERS if ARM && ARCH_EXYNOS
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select MFD_CORE
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# There is no need to enable these drivers for ARMv8
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config EXYNOS_PMU_ARM_DRIVERS
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bool "Exynos PMU ARMv7-specific driver extensions" if COMPILE_TEST
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depends on EXYNOS_PMU
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config EXYNOS_PM_DOMAINS
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bool "Exynos PM domains" if COMPILE_TEST
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depends on (ARCH_EXYNOS && PM_GENERIC_DOMAINS) || COMPILE_TEST
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config SAMSUNG_PM_DEBUG
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bool "Samsung PM Suspend debug"
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depends on PM && DEBUG_KERNEL
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depends on PLAT_S3C24XX || ARCH_S3C64XX || ARCH_S5PV210
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depends on DEBUG_S3C24XX_UART || DEBUG_S3C2410_UART
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depends on DEBUG_LL && MMU
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help
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Say Y here if you want verbose debugging from the PM Suspend and
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Resume code. See <file:Documentation/arm/samsung-s3c24xx/suspend.rst>
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for more information.
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config S3C_PM_DEBUG_LED_SMDK
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bool "SMDK LED suspend/resume debugging"
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depends on PM && (MACH_SMDK6410)
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help
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Say Y here to enable the use of the SMDK LEDs on the baseboard
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for debugging of the state of the suspend and resume process.
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Note, this currently only works for S3C64XX based SMDK boards.
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config SAMSUNG_PM_CHECK
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bool "S3C2410 PM Suspend Memory CRC"
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depends on PM && (PLAT_S3C24XX || ARCH_S3C64XX || ARCH_S5PV210)
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select CRC32
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help
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Enable the PM code's memory area checksum over sleep. This option
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will generate CRCs of all blocks of memory, and store them before
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going to sleep. The blocks are then checked on resume for any
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errors.
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Note, this can take several seconds depending on memory size
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and CPU speed.
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See <file:Documentation/arm/samsung-s3c24xx/suspend.rst>
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config SAMSUNG_PM_CHECK_CHUNKSIZE
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int "S3C2410 PM Suspend CRC Chunksize (KiB)"
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depends on PM && SAMSUNG_PM_CHECK
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default 64
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help
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Set the chunksize in Kilobytes of the CRC for checking memory
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corruption over suspend and resume. A smaller value will mean that
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the CRC data block will take more memory, but will identify any
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faults with better precision.
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See <file:Documentation/arm/samsung-s3c24xx/suspend.rst>
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config EXYNOS_REGULATOR_COUPLER
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bool "Exynos SoC Regulator Coupler" if COMPILE_TEST
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depends on ARCH_EXYNOS || COMPILE_TEST
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endif
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