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340ffd267c
Add a workaround for PowerPC 440EPx/GRx incorrect write to DDR SDRAM errata. Data can be written to wrong address in SDRAM when write pipelining enabled on plb0. We disable it in the cpu_setup for these processors at early init. Signed-off-by: Valentine Barshak <vbarshak@ru.mvista.com> Signed-off-by: Josh Boyer <jwboyer@linux.vnet.ibm.com> |
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boot | ||
configs | ||
kernel | ||
lib | ||
math-emu | ||
mm | ||
oprofile | ||
platforms | ||
sysdev | ||
xmon | ||
.gitignore | ||
Kconfig | ||
Kconfig.debug | ||
Makefile |