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76c567fbba
The Tilera architecture traditionally supports 64KB page sizes to improve TLB utilization and improve performance when the hardware is being used primarily to run a single application. For more generic server scenarios, it can be beneficial to run with 4KB page sizes, so this commit allows that to be specified (by modifying the arch/tile/include/hv/pagesize.h header). As part of this change, we also re-worked the PTE management slightly so that PTE writes all go through a __set_pte() function where we can do some additional validation. The set_pte_order() function was eliminated since the "order" argument wasn't being used. One bug uncovered was in the PCI DMA code, which wasn't properly flushing the specified range. This was benign with 64KB pages, but with 4KB pages we were getting some larger flushes wrong. The per-cpu memory reservation code also needed updating to conform with the newer percpu stuff; before it always chose 64KB, and that was always correct, but with 4KB granularity we now have to pay closer attention and reserve the amount of memory that will be requested when the percpu code starts allocating. Signed-off-by: Chris Metcalf <cmetcalf@tilera.com>
123 lines
3.7 KiB
C
123 lines
3.7 KiB
C
/*
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* Copyright 2010 Tilera Corporation. All Rights Reserved.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License
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* as published by the Free Software Foundation, version 2.
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*
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* This program is distributed in the hope that it will be useful, but
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* WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or
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* NON INFRINGEMENT. See the GNU General Public License for
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* more details.
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*/
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#ifndef _ASM_TILE_PGALLOC_H
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#define _ASM_TILE_PGALLOC_H
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#include <linux/threads.h>
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#include <linux/mm.h>
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#include <linux/mmzone.h>
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#include <asm/fixmap.h>
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#include <hv/hypervisor.h>
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/* Bits for the size of the second-level page table. */
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#define L2_KERNEL_PGTABLE_SHIFT \
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(HV_LOG2_PAGE_SIZE_LARGE - HV_LOG2_PAGE_SIZE_SMALL + HV_LOG2_PTE_SIZE)
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/* We currently allocate user L2 page tables by page (unlike kernel L2s). */
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#if L2_KERNEL_PGTABLE_SHIFT < HV_LOG2_PAGE_SIZE_SMALL
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#define L2_USER_PGTABLE_SHIFT HV_LOG2_PAGE_SIZE_SMALL
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#else
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#define L2_USER_PGTABLE_SHIFT L2_KERNEL_PGTABLE_SHIFT
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#endif
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/* How many pages do we need, as an "order", for a user L2 page table? */
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#define L2_USER_PGTABLE_ORDER (L2_USER_PGTABLE_SHIFT - HV_LOG2_PAGE_SIZE_SMALL)
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/* How big is a kernel L2 page table? */
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#define L2_KERNEL_PGTABLE_SIZE (1 << L2_KERNEL_PGTABLE_SHIFT)
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static inline void set_pmd(pmd_t *pmdp, pmd_t pmd)
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{
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#ifdef CONFIG_64BIT
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set_pte(pmdp, pmd);
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#else
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set_pte(&pmdp->pud.pgd, pmd.pud.pgd);
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#endif
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}
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static inline void pmd_populate_kernel(struct mm_struct *mm,
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pmd_t *pmd, pte_t *ptep)
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{
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set_pmd(pmd, ptfn_pmd(__pa(ptep) >> HV_LOG2_PAGE_TABLE_ALIGN,
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__pgprot(_PAGE_PRESENT)));
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}
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static inline void pmd_populate(struct mm_struct *mm, pmd_t *pmd,
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pgtable_t page)
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{
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set_pmd(pmd, ptfn_pmd(HV_PFN_TO_PTFN(page_to_pfn(page)),
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__pgprot(_PAGE_PRESENT)));
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}
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/*
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* Allocate and free page tables.
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*/
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extern pgd_t *pgd_alloc(struct mm_struct *mm);
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extern void pgd_free(struct mm_struct *mm, pgd_t *pgd);
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extern pgtable_t pte_alloc_one(struct mm_struct *mm, unsigned long address);
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extern void pte_free(struct mm_struct *mm, struct page *pte);
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#define pmd_pgtable(pmd) pmd_page(pmd)
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static inline pte_t *
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pte_alloc_one_kernel(struct mm_struct *mm, unsigned long address)
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{
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return pfn_to_kaddr(page_to_pfn(pte_alloc_one(mm, address)));
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}
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static inline void pte_free_kernel(struct mm_struct *mm, pte_t *pte)
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{
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BUG_ON((unsigned long)pte & (PAGE_SIZE-1));
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pte_free(mm, virt_to_page(pte));
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}
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extern void __pte_free_tlb(struct mmu_gather *tlb, struct page *pte,
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unsigned long address);
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#define check_pgt_cache() do { } while (0)
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/*
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* Get the small-page pte_t lowmem entry for a given pfn.
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* This may or may not be in use, depending on whether the initial
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* huge-page entry for the page has already been shattered.
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*/
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pte_t *get_prealloc_pte(unsigned long pfn);
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/* During init, we can shatter kernel huge pages if needed. */
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void shatter_pmd(pmd_t *pmd);
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/* After init, a more complex technique is required. */
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void shatter_huge_page(unsigned long addr);
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#ifdef __tilegx__
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/* We share a single page allocator for both L1 and L2 page tables. */
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#if HV_L1_SIZE != HV_L2_SIZE
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# error Rework assumption that L1 and L2 page tables are same size.
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#endif
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#define L1_USER_PGTABLE_ORDER L2_USER_PGTABLE_ORDER
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#define pud_populate(mm, pud, pmd) \
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pmd_populate_kernel((mm), (pmd_t *)(pud), (pte_t *)(pmd))
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#define pmd_alloc_one(mm, addr) \
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((pmd_t *)page_to_virt(pte_alloc_one((mm), (addr))))
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#define pmd_free(mm, pmdp) \
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pte_free((mm), virt_to_page(pmdp))
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#define __pmd_free_tlb(tlb, pmdp, address) \
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__pte_free_tlb((tlb), virt_to_page(pmdp), (address))
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#endif
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#endif /* _ASM_TILE_PGALLOC_H */
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