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b24413180f
Many source files in the tree are missing licensing information, which makes it harder for compliance tools to determine the correct license. By default all files without license information are under the default license of the kernel, which is GPL version 2. Update the files which contain no license information with the 'GPL-2.0' SPDX license identifier. The SPDX identifier is a legally binding shorthand, which can be used instead of the full boiler plate text. This patch is based on work done by Thomas Gleixner and Kate Stewart and Philippe Ombredanne. How this work was done: Patches were generated and checked against linux-4.14-rc6 for a subset of the use cases: - file had no licensing information it it. - file was a */uapi/* one with no licensing information in it, - file was a */uapi/* one with existing licensing information, Further patches will be generated in subsequent months to fix up cases where non-standard license headers were used, and references to license had to be inferred by heuristics based on keywords. The analysis to determine which SPDX License Identifier to be applied to a file was done in a spreadsheet of side by side results from of the output of two independent scanners (ScanCode & Windriver) producing SPDX tag:value files created by Philippe Ombredanne. Philippe prepared the base worksheet, and did an initial spot review of a few 1000 files. The 4.13 kernel was the starting point of the analysis with 60,537 files assessed. Kate Stewart did a file by file comparison of the scanner results in the spreadsheet to determine which SPDX license identifier(s) to be applied to the file. She confirmed any determination that was not immediately clear with lawyers working with the Linux Foundation. Criteria used to select files for SPDX license identifier tagging was: - Files considered eligible had to be source code files. - Make and config files were included as candidates if they contained >5 lines of source - File already had some variant of a license header in it (even if <5 lines). All documentation files were explicitly excluded. The following heuristics were used to determine which SPDX license identifiers to apply. - when both scanners couldn't find any license traces, file was considered to have no license information in it, and the top level COPYING file license applied. For non */uapi/* files that summary was: SPDX license identifier # files ---------------------------------------------------|------- GPL-2.0 11139 and resulted in the first patch in this series. If that file was a */uapi/* path one, it was "GPL-2.0 WITH Linux-syscall-note" otherwise it was "GPL-2.0". Results of that was: SPDX license identifier # files ---------------------------------------------------|------- GPL-2.0 WITH Linux-syscall-note 930 and resulted in the second patch in this series. - if a file had some form of licensing information in it, and was one of the */uapi/* ones, it was denoted with the Linux-syscall-note if any GPL family license was found in the file or had no licensing in it (per prior point). Results summary: SPDX license identifier # files ---------------------------------------------------|------ GPL-2.0 WITH Linux-syscall-note 270 GPL-2.0+ WITH Linux-syscall-note 169 ((GPL-2.0 WITH Linux-syscall-note) OR BSD-2-Clause) 21 ((GPL-2.0 WITH Linux-syscall-note) OR BSD-3-Clause) 17 LGPL-2.1+ WITH Linux-syscall-note 15 GPL-1.0+ WITH Linux-syscall-note 14 ((GPL-2.0+ WITH Linux-syscall-note) OR BSD-3-Clause) 5 LGPL-2.0+ WITH Linux-syscall-note 4 LGPL-2.1 WITH Linux-syscall-note 3 ((GPL-2.0 WITH Linux-syscall-note) OR MIT) 3 ((GPL-2.0 WITH Linux-syscall-note) AND MIT) 1 and that resulted in the third patch in this series. - when the two scanners agreed on the detected license(s), that became the concluded license(s). - when there was disagreement between the two scanners (one detected a license but the other didn't, or they both detected different licenses) a manual inspection of the file occurred. - In most cases a manual inspection of the information in the file resulted in a clear resolution of the license that should apply (and which scanner probably needed to revisit its heuristics). - When it was not immediately clear, the license identifier was confirmed with lawyers working with the Linux Foundation. - If there was any question as to the appropriate license identifier, the file was flagged for further research and to be revisited later in time. In total, over 70 hours of logged manual review was done on the spreadsheet to determine the SPDX license identifiers to apply to the source files by Kate, Philippe, Thomas and, in some cases, confirmation by lawyers working with the Linux Foundation. Kate also obtained a third independent scan of the 4.13 code base from FOSSology, and compared selected files where the other two scanners disagreed against that SPDX file, to see if there was new insights. The Windriver scanner is based on an older version of FOSSology in part, so they are related. Thomas did random spot checks in about 500 files from the spreadsheets for the uapi headers and agreed with SPDX license identifier in the files he inspected. For the non-uapi files Thomas did random spot checks in about 15000 files. In initial set of patches against 4.14-rc6, 3 files were found to have copy/paste license identifier errors, and have been fixed to reflect the correct identifier. Additionally Philippe spent 10 hours this week doing a detailed manual inspection and review of the 12,461 patched files from the initial patch version early this week with: - a full scancode scan run, collecting the matched texts, detected license ids and scores - reviewing anything where there was a license detected (about 500+ files) to ensure that the applied SPDX license was correct - reviewing anything where there was no detection but the patch license was not GPL-2.0 WITH Linux-syscall-note to ensure that the applied SPDX license was correct This produced a worksheet with 20 files needing minor correction. This worksheet was then exported into 3 different .csv files for the different types of files to be modified. These .csv files were then reviewed by Greg. Thomas wrote a script to parse the csv files and add the proper SPDX tag to the file, in the format that the file expected. This script was further refined by Greg based on the output to detect more types of files automatically and to distinguish between header and source .c files (which need different comment types.) Finally Greg ran the script using the .csv files to generate the patches. Reviewed-by: Kate Stewart <kstewart@linuxfoundation.org> Reviewed-by: Philippe Ombredanne <pombredanne@nexb.com> Reviewed-by: Thomas Gleixner <tglx@linutronix.de> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
438 lines
15 KiB
C
438 lines
15 KiB
C
/* SPDX-License-Identifier: GPL-2.0 */
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/*
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* cpu.h: Values of the PRId register used to match up
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* various MIPS cpu types.
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*
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* Copyright (C) 1996 David S. Miller (davem@davemloft.net)
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* Copyright (C) 2004, 2013 Maciej W. Rozycki
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*/
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#ifndef _ASM_CPU_H
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#define _ASM_CPU_H
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/*
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As of the MIPS32 and MIPS64 specs from MTI, the PRId register (CP0
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register 15, select 0) is defined in this (backwards compatible) way:
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+----------------+----------------+----------------+----------------+
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| Company Options| Company ID | Processor ID | Revision |
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+----------------+----------------+----------------+----------------+
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31 24 23 16 15 8 7
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I don't have docs for all the previous processors, but my impression is
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that bits 16-23 have been 0 for all MIPS processors before the MIPS32/64
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spec.
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*/
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#define PRID_OPT_MASK 0xff000000
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/*
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* Assigned Company values for bits 23:16 of the PRId register.
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*/
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#define PRID_COMP_MASK 0xff0000
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#define PRID_COMP_LEGACY 0x000000
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#define PRID_COMP_MIPS 0x010000
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#define PRID_COMP_BROADCOM 0x020000
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#define PRID_COMP_ALCHEMY 0x030000
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#define PRID_COMP_SIBYTE 0x040000
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#define PRID_COMP_SANDCRAFT 0x050000
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#define PRID_COMP_NXP 0x060000
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#define PRID_COMP_TOSHIBA 0x070000
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#define PRID_COMP_LSI 0x080000
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#define PRID_COMP_LEXRA 0x0b0000
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#define PRID_COMP_NETLOGIC 0x0c0000
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#define PRID_COMP_CAVIUM 0x0d0000
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#define PRID_COMP_LOONGSON 0x140000
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#define PRID_COMP_INGENIC_D0 0xd00000 /* JZ4740, JZ4750 */
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#define PRID_COMP_INGENIC_D1 0xd10000 /* JZ4770, JZ4775 */
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#define PRID_COMP_INGENIC_E1 0xe10000 /* JZ4780 */
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/*
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* Assigned Processor ID (implementation) values for bits 15:8 of the PRId
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* register. In order to detect a certain CPU type exactly eventually
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* additional registers may need to be examined.
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*/
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#define PRID_IMP_MASK 0xff00
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/*
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* These are valid when 23:16 == PRID_COMP_LEGACY
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*/
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#define PRID_IMP_R2000 0x0100
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#define PRID_IMP_AU1_REV1 0x0100
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#define PRID_IMP_AU1_REV2 0x0200
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#define PRID_IMP_R3000 0x0200 /* Same as R2000A */
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#define PRID_IMP_R6000 0x0300 /* Same as R3000A */
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#define PRID_IMP_R4000 0x0400
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#define PRID_IMP_R6000A 0x0600
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#define PRID_IMP_R10000 0x0900
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#define PRID_IMP_R4300 0x0b00
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#define PRID_IMP_VR41XX 0x0c00
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#define PRID_IMP_R12000 0x0e00
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#define PRID_IMP_R14000 0x0f00 /* R14K && R16K */
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#define PRID_IMP_R8000 0x1000
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#define PRID_IMP_PR4450 0x1200
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#define PRID_IMP_R4600 0x2000
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#define PRID_IMP_R4700 0x2100
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#define PRID_IMP_TX39 0x2200
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#define PRID_IMP_R4640 0x2200
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#define PRID_IMP_R4650 0x2200 /* Same as R4640 */
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#define PRID_IMP_R5000 0x2300
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#define PRID_IMP_TX49 0x2d00
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#define PRID_IMP_SONIC 0x2400
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#define PRID_IMP_MAGIC 0x2500
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#define PRID_IMP_RM7000 0x2700
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#define PRID_IMP_NEVADA 0x2800 /* RM5260 ??? */
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#define PRID_IMP_RM9000 0x3400
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#define PRID_IMP_LOONGSON_32 0x4200 /* Loongson-1 */
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#define PRID_IMP_R5432 0x5400
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#define PRID_IMP_R5500 0x5500
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#define PRID_IMP_LOONGSON_64 0x6300 /* Loongson-2/3 */
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#define PRID_IMP_UNKNOWN 0xff00
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/*
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* These are the PRID's for when 23:16 == PRID_COMP_MIPS
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*/
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#define PRID_IMP_QEMU_GENERIC 0x0000
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#define PRID_IMP_4KC 0x8000
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#define PRID_IMP_5KC 0x8100
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#define PRID_IMP_20KC 0x8200
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#define PRID_IMP_4KEC 0x8400
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#define PRID_IMP_4KSC 0x8600
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#define PRID_IMP_25KF 0x8800
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#define PRID_IMP_5KE 0x8900
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#define PRID_IMP_4KECR2 0x9000
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#define PRID_IMP_4KEMPR2 0x9100
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#define PRID_IMP_4KSD 0x9200
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#define PRID_IMP_24K 0x9300
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#define PRID_IMP_34K 0x9500
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#define PRID_IMP_24KE 0x9600
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#define PRID_IMP_74K 0x9700
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#define PRID_IMP_1004K 0x9900
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#define PRID_IMP_1074K 0x9a00
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#define PRID_IMP_M14KC 0x9c00
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#define PRID_IMP_M14KEC 0x9e00
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#define PRID_IMP_INTERAPTIV_UP 0xa000
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#define PRID_IMP_INTERAPTIV_MP 0xa100
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#define PRID_IMP_PROAPTIV_UP 0xa200
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#define PRID_IMP_PROAPTIV_MP 0xa300
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#define PRID_IMP_P6600 0xa400
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#define PRID_IMP_M5150 0xa700
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#define PRID_IMP_P5600 0xa800
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#define PRID_IMP_I6400 0xa900
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#define PRID_IMP_M6250 0xab00
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#define PRID_IMP_I6500 0xb000
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/*
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* These are the PRID's for when 23:16 == PRID_COMP_SIBYTE
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*/
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#define PRID_IMP_SB1 0x0100
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#define PRID_IMP_SB1A 0x1100
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/*
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* These are the PRID's for when 23:16 == PRID_COMP_SANDCRAFT
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*/
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#define PRID_IMP_SR71000 0x0400
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/*
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* These are the PRID's for when 23:16 == PRID_COMP_BROADCOM
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*/
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#define PRID_IMP_BMIPS32_REV4 0x4000
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#define PRID_IMP_BMIPS32_REV8 0x8000
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#define PRID_IMP_BMIPS3300 0x9000
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#define PRID_IMP_BMIPS3300_ALT 0x9100
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#define PRID_IMP_BMIPS3300_BUG 0x0000
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#define PRID_IMP_BMIPS43XX 0xa000
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#define PRID_IMP_BMIPS5000 0x5a00
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#define PRID_IMP_BMIPS5200 0x5b00
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#define PRID_REV_BMIPS4380_LO 0x0040
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#define PRID_REV_BMIPS4380_HI 0x006f
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/*
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* These are the PRID's for when 23:16 == PRID_COMP_CAVIUM
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*/
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#define PRID_IMP_CAVIUM_CN38XX 0x0000
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#define PRID_IMP_CAVIUM_CN31XX 0x0100
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#define PRID_IMP_CAVIUM_CN30XX 0x0200
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#define PRID_IMP_CAVIUM_CN58XX 0x0300
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#define PRID_IMP_CAVIUM_CN56XX 0x0400
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#define PRID_IMP_CAVIUM_CN50XX 0x0600
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#define PRID_IMP_CAVIUM_CN52XX 0x0700
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#define PRID_IMP_CAVIUM_CN63XX 0x9000
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#define PRID_IMP_CAVIUM_CN68XX 0x9100
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#define PRID_IMP_CAVIUM_CN66XX 0x9200
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#define PRID_IMP_CAVIUM_CN61XX 0x9300
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#define PRID_IMP_CAVIUM_CNF71XX 0x9400
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#define PRID_IMP_CAVIUM_CN78XX 0x9500
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#define PRID_IMP_CAVIUM_CN70XX 0x9600
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#define PRID_IMP_CAVIUM_CN73XX 0x9700
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#define PRID_IMP_CAVIUM_CNF75XX 0x9800
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/*
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* These are the PRID's for when 23:16 == PRID_COMP_INGENIC_*
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*/
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#define PRID_IMP_JZRISC 0x0200
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/*
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* These are the PRID's for when 23:16 == PRID_COMP_NETLOGIC
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*/
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#define PRID_IMP_NETLOGIC_XLR732 0x0000
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#define PRID_IMP_NETLOGIC_XLR716 0x0200
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#define PRID_IMP_NETLOGIC_XLR532 0x0900
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#define PRID_IMP_NETLOGIC_XLR308 0x0600
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#define PRID_IMP_NETLOGIC_XLR532C 0x0800
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#define PRID_IMP_NETLOGIC_XLR516C 0x0a00
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#define PRID_IMP_NETLOGIC_XLR508C 0x0b00
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#define PRID_IMP_NETLOGIC_XLR308C 0x0f00
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#define PRID_IMP_NETLOGIC_XLS608 0x8000
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#define PRID_IMP_NETLOGIC_XLS408 0x8800
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#define PRID_IMP_NETLOGIC_XLS404 0x8c00
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#define PRID_IMP_NETLOGIC_XLS208 0x8e00
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#define PRID_IMP_NETLOGIC_XLS204 0x8f00
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#define PRID_IMP_NETLOGIC_XLS108 0xce00
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#define PRID_IMP_NETLOGIC_XLS104 0xcf00
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#define PRID_IMP_NETLOGIC_XLS616B 0x4000
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#define PRID_IMP_NETLOGIC_XLS608B 0x4a00
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#define PRID_IMP_NETLOGIC_XLS416B 0x4400
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#define PRID_IMP_NETLOGIC_XLS412B 0x4c00
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#define PRID_IMP_NETLOGIC_XLS408B 0x4e00
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#define PRID_IMP_NETLOGIC_XLS404B 0x4f00
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#define PRID_IMP_NETLOGIC_AU13XX 0x8000
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#define PRID_IMP_NETLOGIC_XLP8XX 0x1000
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#define PRID_IMP_NETLOGIC_XLP3XX 0x1100
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#define PRID_IMP_NETLOGIC_XLP2XX 0x1200
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#define PRID_IMP_NETLOGIC_XLP9XX 0x1500
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#define PRID_IMP_NETLOGIC_XLP5XX 0x1300
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/*
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* Particular Revision values for bits 7:0 of the PRId register.
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*/
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#define PRID_REV_MASK 0x00ff
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/*
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* Definitions for 7:0 on legacy processors
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*/
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#define PRID_REV_TX4927 0x0022
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#define PRID_REV_TX4937 0x0030
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#define PRID_REV_R4400 0x0040
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#define PRID_REV_R3000A 0x0030
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#define PRID_REV_R3000 0x0020
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#define PRID_REV_R2000A 0x0010
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#define PRID_REV_TX3912 0x0010
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#define PRID_REV_TX3922 0x0030
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#define PRID_REV_TX3927 0x0040
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#define PRID_REV_VR4111 0x0050
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#define PRID_REV_VR4181 0x0050 /* Same as VR4111 */
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#define PRID_REV_VR4121 0x0060
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#define PRID_REV_VR4122 0x0070
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#define PRID_REV_VR4181A 0x0070 /* Same as VR4122 */
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#define PRID_REV_VR4130 0x0080
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#define PRID_REV_34K_V1_0_2 0x0022
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#define PRID_REV_LOONGSON1B 0x0020
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#define PRID_REV_LOONGSON1C 0x0020 /* Same as Loongson-1B */
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#define PRID_REV_LOONGSON2E 0x0002
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#define PRID_REV_LOONGSON2F 0x0003
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#define PRID_REV_LOONGSON3A_R1 0x0005
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#define PRID_REV_LOONGSON3B_R1 0x0006
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#define PRID_REV_LOONGSON3B_R2 0x0007
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#define PRID_REV_LOONGSON3A_R2 0x0008
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#define PRID_REV_LOONGSON3A_R3 0x0009
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/*
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* Older processors used to encode processor version and revision in two
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* 4-bit bitfields, the 4K seems to simply count up and even newer MTI cores
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* have switched to use the 8-bits as 3:3:2 bitfield with the last field as
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* the patch number. *ARGH*
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*/
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#define PRID_REV_ENCODE_44(ver, rev) \
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((ver) << 4 | (rev))
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#define PRID_REV_ENCODE_332(ver, rev, patch) \
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((ver) << 5 | (rev) << 2 | (patch))
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/*
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* FPU implementation/revision register (CP1 control register 0).
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*
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* +---------------------------------+----------------+----------------+
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* | 0 | Implementation | Revision |
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* +---------------------------------+----------------+----------------+
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* 31 16 15 8 7 0
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*/
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#define FPIR_IMP_MASK 0xff00
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#define FPIR_IMP_NONE 0x0000
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#if !defined(__ASSEMBLY__)
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enum cpu_type_enum {
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CPU_UNKNOWN,
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/*
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* R2000 class processors
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*/
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CPU_R2000, CPU_R3000, CPU_R3000A, CPU_R3041, CPU_R3051, CPU_R3052,
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CPU_R3081, CPU_R3081E,
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/*
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* R4000 class processors
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*/
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CPU_R4000PC, CPU_R4000SC, CPU_R4000MC, CPU_R4200, CPU_R4300, CPU_R4310,
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CPU_R4400PC, CPU_R4400SC, CPU_R4400MC, CPU_R4600, CPU_R4640, CPU_R4650,
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CPU_R4700, CPU_R5000, CPU_R5500, CPU_NEVADA, CPU_R5432, CPU_R10000,
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CPU_R12000, CPU_R14000, CPU_R16000, CPU_VR41XX, CPU_VR4111, CPU_VR4121,
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CPU_VR4122, CPU_VR4131, CPU_VR4133, CPU_VR4181, CPU_VR4181A, CPU_RM7000,
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CPU_SR71000, CPU_TX49XX,
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/*
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* R8000 class processors
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*/
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CPU_R8000,
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/*
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* TX3900 class processors
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*/
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CPU_TX3912, CPU_TX3922, CPU_TX3927,
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/*
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* MIPS32 class processors
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*/
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CPU_4KC, CPU_4KEC, CPU_4KSC, CPU_24K, CPU_34K, CPU_1004K, CPU_74K,
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CPU_ALCHEMY, CPU_PR4450, CPU_BMIPS32, CPU_BMIPS3300, CPU_BMIPS4350,
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CPU_BMIPS4380, CPU_BMIPS5000, CPU_JZRISC, CPU_LOONGSON1, CPU_M14KC,
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CPU_M14KEC, CPU_INTERAPTIV, CPU_P5600, CPU_PROAPTIV, CPU_1074K,
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CPU_M5150, CPU_I6400, CPU_P6600, CPU_M6250,
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/*
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* MIPS64 class processors
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*/
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CPU_5KC, CPU_5KE, CPU_20KC, CPU_25KF, CPU_SB1, CPU_SB1A, CPU_LOONGSON2,
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CPU_LOONGSON3, CPU_CAVIUM_OCTEON, CPU_CAVIUM_OCTEON_PLUS,
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CPU_CAVIUM_OCTEON2, CPU_CAVIUM_OCTEON3, CPU_XLR, CPU_XLP, CPU_I6500,
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CPU_QEMU_GENERIC,
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CPU_LAST
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};
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#endif /* !__ASSEMBLY */
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/*
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* ISA Level encodings
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*
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*/
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#define MIPS_CPU_ISA_II 0x00000001
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#define MIPS_CPU_ISA_III 0x00000002
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#define MIPS_CPU_ISA_IV 0x00000004
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#define MIPS_CPU_ISA_V 0x00000008
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#define MIPS_CPU_ISA_M32R1 0x00000010
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#define MIPS_CPU_ISA_M32R2 0x00000020
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#define MIPS_CPU_ISA_M64R1 0x00000040
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#define MIPS_CPU_ISA_M64R2 0x00000080
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#define MIPS_CPU_ISA_M32R6 0x00000100
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#define MIPS_CPU_ISA_M64R6 0x00000200
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#define MIPS_CPU_ISA_32BIT (MIPS_CPU_ISA_II | MIPS_CPU_ISA_M32R1 | \
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MIPS_CPU_ISA_M32R2 | MIPS_CPU_ISA_M32R6)
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#define MIPS_CPU_ISA_64BIT (MIPS_CPU_ISA_III | MIPS_CPU_ISA_IV | \
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MIPS_CPU_ISA_V | MIPS_CPU_ISA_M64R1 | MIPS_CPU_ISA_M64R2 | \
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MIPS_CPU_ISA_M64R6)
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/*
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* Private version of BIT_ULL() to escape include file recursion hell.
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* We soon will have to switch to another mechanism that will work with
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* more than 64 bits anyway.
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*/
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#define MBIT_ULL(bit) (1ULL << (bit))
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/*
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* CPU Option encodings
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*/
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#define MIPS_CPU_TLB MBIT_ULL( 0) /* CPU has TLB */
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#define MIPS_CPU_4KEX MBIT_ULL( 1) /* "R4K" exception model */
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#define MIPS_CPU_3K_CACHE MBIT_ULL( 2) /* R3000-style caches */
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#define MIPS_CPU_4K_CACHE MBIT_ULL( 3) /* R4000-style caches */
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#define MIPS_CPU_TX39_CACHE MBIT_ULL( 4) /* TX3900-style caches */
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#define MIPS_CPU_FPU MBIT_ULL( 5) /* CPU has FPU */
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#define MIPS_CPU_32FPR MBIT_ULL( 6) /* 32 dbl. prec. FP registers */
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#define MIPS_CPU_COUNTER MBIT_ULL( 7) /* Cycle count/compare */
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#define MIPS_CPU_WATCH MBIT_ULL( 8) /* watchpoint registers */
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#define MIPS_CPU_DIVEC MBIT_ULL( 9) /* dedicated interrupt vector */
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#define MIPS_CPU_VCE MBIT_ULL(10) /* virt. coherence conflict possible */
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#define MIPS_CPU_CACHE_CDEX_P MBIT_ULL(11) /* Create_Dirty_Exclusive CACHE op */
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#define MIPS_CPU_CACHE_CDEX_S MBIT_ULL(12) /* ... same for seconary cache ... */
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#define MIPS_CPU_MCHECK MBIT_ULL(13) /* Machine check exception */
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#define MIPS_CPU_EJTAG MBIT_ULL(14) /* EJTAG exception */
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#define MIPS_CPU_NOFPUEX MBIT_ULL(15) /* no FPU exception */
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#define MIPS_CPU_LLSC MBIT_ULL(16) /* CPU has ll/sc instructions */
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#define MIPS_CPU_INCLUSIVE_CACHES MBIT_ULL(17) /* P-cache subset enforced */
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#define MIPS_CPU_PREFETCH MBIT_ULL(18) /* CPU has usable prefetch */
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#define MIPS_CPU_VINT MBIT_ULL(19) /* CPU supports MIPSR2 vectored interrupts */
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#define MIPS_CPU_VEIC MBIT_ULL(20) /* CPU supports MIPSR2 external interrupt controller mode */
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#define MIPS_CPU_ULRI MBIT_ULL(21) /* CPU has ULRI feature */
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#define MIPS_CPU_PCI MBIT_ULL(22) /* CPU has Perf Ctr Int indicator */
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#define MIPS_CPU_RIXI MBIT_ULL(23) /* CPU has TLB Read/eXec Inhibit */
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#define MIPS_CPU_MICROMIPS MBIT_ULL(24) /* CPU has microMIPS capability */
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#define MIPS_CPU_TLBINV MBIT_ULL(25) /* CPU supports TLBINV/F */
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#define MIPS_CPU_SEGMENTS MBIT_ULL(26) /* CPU supports Segmentation Control registers */
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#define MIPS_CPU_EVA MBIT_ULL(27) /* CPU supports Enhanced Virtual Addressing */
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#define MIPS_CPU_HTW MBIT_ULL(28) /* CPU support Hardware Page Table Walker */
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#define MIPS_CPU_RIXIEX MBIT_ULL(29) /* CPU has unique exception codes for {Read, Execute}-Inhibit exceptions */
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#define MIPS_CPU_MAAR MBIT_ULL(30) /* MAAR(I) registers are present */
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#define MIPS_CPU_FRE MBIT_ULL(31) /* FRE & UFE bits implemented */
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#define MIPS_CPU_RW_LLB MBIT_ULL(32) /* LLADDR/LLB writes are allowed */
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#define MIPS_CPU_LPA MBIT_ULL(33) /* CPU supports Large Physical Addressing */
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#define MIPS_CPU_CDMM MBIT_ULL(34) /* CPU has Common Device Memory Map */
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#define MIPS_CPU_BP_GHIST MBIT_ULL(35) /* R12K+ Branch Prediction Global History */
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#define MIPS_CPU_SP MBIT_ULL(36) /* Small (1KB) page support */
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#define MIPS_CPU_FTLB MBIT_ULL(37) /* CPU has Fixed-page-size TLB */
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#define MIPS_CPU_NAN_LEGACY MBIT_ULL(38) /* Legacy NaN implemented */
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#define MIPS_CPU_NAN_2008 MBIT_ULL(39) /* 2008 NaN implemented */
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#define MIPS_CPU_VP MBIT_ULL(40) /* MIPSr6 Virtual Processors (multi-threading) */
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#define MIPS_CPU_LDPTE MBIT_ULL(41) /* CPU has ldpte/lddir instructions */
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#define MIPS_CPU_MVH MBIT_ULL(42) /* CPU supports MFHC0/MTHC0 */
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#define MIPS_CPU_EBASE_WG MBIT_ULL(43) /* CPU has EBase.WG */
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#define MIPS_CPU_BADINSTR MBIT_ULL(44) /* CPU has BadInstr register */
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#define MIPS_CPU_BADINSTRP MBIT_ULL(45) /* CPU has BadInstrP register */
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#define MIPS_CPU_CTXTC MBIT_ULL(46) /* CPU has [X]ConfigContext registers */
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#define MIPS_CPU_PERF MBIT_ULL(47) /* CPU has MIPS performance counters */
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#define MIPS_CPU_GUESTCTL0EXT MBIT_ULL(48) /* CPU has VZ GuestCtl0Ext register */
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#define MIPS_CPU_GUESTCTL1 MBIT_ULL(49) /* CPU has VZ GuestCtl1 register */
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#define MIPS_CPU_GUESTCTL2 MBIT_ULL(50) /* CPU has VZ GuestCtl2 register */
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#define MIPS_CPU_GUESTID MBIT_ULL(51) /* CPU uses VZ ASE GuestID feature */
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#define MIPS_CPU_DRG MBIT_ULL(52) /* CPU has VZ Direct Root to Guest (DRG) */
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#define MIPS_CPU_UFR MBIT_ULL(53) /* CPU supports User mode FR switching */
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#define MIPS_CPU_SHARED_FTLB_RAM \
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MBIT_ULL(54) /* CPU shares FTLB RAM with another */
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#define MIPS_CPU_SHARED_FTLB_ENTRIES \
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MBIT_ULL(55) /* CPU shares FTLB entries with another */
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/*
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* CPU ASE encodings
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*/
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#define MIPS_ASE_MIPS16 0x00000001 /* code compression */
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#define MIPS_ASE_MDMX 0x00000002 /* MIPS digital media extension */
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#define MIPS_ASE_MIPS3D 0x00000004 /* MIPS-3D */
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#define MIPS_ASE_SMARTMIPS 0x00000008 /* SmartMIPS */
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#define MIPS_ASE_DSP 0x00000010 /* Signal Processing ASE */
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#define MIPS_ASE_MIPSMT 0x00000020 /* CPU supports MIPS MT */
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#define MIPS_ASE_DSP2P 0x00000040 /* Signal Processing ASE Rev 2 */
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#define MIPS_ASE_VZ 0x00000080 /* Virtualization ASE */
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#define MIPS_ASE_MSA 0x00000100 /* MIPS SIMD Architecture */
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#define MIPS_ASE_DSP3 0x00000200 /* Signal Processing ASE Rev 3*/
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#define MIPS_ASE_MIPS16E2 0x00000400 /* MIPS16e2 */
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#endif /* _ASM_CPU_H */
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