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The VCLK and VCLK_DIV clocks have supplementary bits. The VCLK gate has a "SOFT RESET" bit to toggle after the whole VCLK sub-tree rate has been set, this is implemented in the gate enable callback. The VCLK_DIV clocks as enable and reset bits used to disable and reset the divider, associated with CLK_SET_RATE_GATE it ensures the rate is set while the divider is disabled and in reset mode. The VCLK_DIV enable bit isn't implemented as a gate since it's part of the divider logic and vendor does this exact sequence to ensure the divider is correctly set. Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org> Link: https://lore.kernel.org/r/20240403-amlogic-v6-4-upstream-dsi-ccf-vim3-v12-2-99ecdfdc87fc@linaro.org Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
52 lines
1.1 KiB
C
52 lines
1.1 KiB
C
/* SPDX-License-Identifier: GPL-2.0 */
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/*
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* Copyright (c) 2024 Neil Armstrong <neil.armstrong@linaro.org>
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*/
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#ifndef __VCLK_H
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#define __VCLK_H
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#include "clk-regmap.h"
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#include "parm.h"
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/**
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* struct meson_vclk_gate_data - vclk_gate regmap backed specific data
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*
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* @enable: vclk enable field
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* @reset: vclk reset field
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* @flags: hardware-specific flags
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*
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* Flags:
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* Same as clk_gate except CLK_GATE_HIWORD_MASK which is ignored
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*/
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struct meson_vclk_gate_data {
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struct parm enable;
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struct parm reset;
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u8 flags;
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};
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extern const struct clk_ops meson_vclk_gate_ops;
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/**
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* struct meson_vclk_div_data - vclk_div regmap back specific data
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*
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* @div: divider field
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* @enable: vclk divider enable field
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* @reset: vclk divider reset field
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* @table: array of value/divider pairs, last entry should have div = 0
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*
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* Flags:
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* Same as clk_divider except CLK_DIVIDER_HIWORD_MASK which is ignored
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*/
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struct meson_vclk_div_data {
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struct parm div;
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struct parm enable;
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struct parm reset;
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const struct clk_div_table *table;
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u8 flags;
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};
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extern const struct clk_ops meson_vclk_div_ops;
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#endif /* __VCLK_H */
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