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In order to support new chip rts5228, the definitions of some internal registers and workflow have to be modified. Added rts5228.c rts5228.h for independent functions of the new chip rts5228 Signed-off-by: Ricky Wu <ricky_wu@realtek.com> Link: https://lore.kernel.org/r/20200706070259.32565-1-ricky_wu@realtek.com Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
169 lines
5.2 KiB
C
169 lines
5.2 KiB
C
/* SPDX-License-Identifier: GPL-2.0-only */
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/* Driver for Realtek PCI-Express card reader
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*
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* Copyright(c) 2018-2019 Realtek Semiconductor Corp. All rights reserved.
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*
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* Author:
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* Ricky WU <ricky_wu@realtek.com>
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* Rui FENG <rui_feng@realsil.com.cn>
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* Wei WANG <wei_wang@realsil.com.cn>
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*/
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#ifndef RTS5228_H
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#define RTS5228_H
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#define RTS5228_AUTOLOAD_CFG0 0xFF7B
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#define RTS5228_AUTOLOAD_CFG1 0xFF7C
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#define RTS5228_AUTOLOAD_CFG2 0xFF7D
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#define RTS5228_AUTOLOAD_CFG3 0xFF7E
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#define RTS5228_AUTOLOAD_CFG4 0xFF7F
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#define RTS5228_REG_VREF 0xFE97
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#define RTS5228_PWD_SUSPND_EN (1 << 4)
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#define RTS5228_PAD_H3L1 0xFF79
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#define PAD_GPIO_H3L1 (1 << 3)
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/* SSC_CTL2 0xFC12 */
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#define RTS5228_SSC_DEPTH_MASK 0x07
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#define RTS5228_SSC_DEPTH_DISALBE 0x00
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#define RTS5228_SSC_DEPTH_8M 0x01
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#define RTS5228_SSC_DEPTH_4M 0x02
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#define RTS5228_SSC_DEPTH_2M 0x03
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#define RTS5228_SSC_DEPTH_1M 0x04
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#define RTS5228_SSC_DEPTH_512K 0x05
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#define RTS5228_SSC_DEPTH_256K 0x06
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#define RTS5228_SSC_DEPTH_128K 0x07
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/* DMACTL 0xFE2C */
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#define RTS5228_DMA_PACK_SIZE_MASK 0xF0
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#define RTS5228_REG_LDO12_CFG 0xFF6E
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#define RTS5228_LDO12_VO_TUNE_MASK (0x07<<1)
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#define RTS5228_LDO12_100 (0x00<<1)
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#define RTS5228_LDO12_105 (0x01<<1)
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#define RTS5228_LDO12_110 (0x02<<1)
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#define RTS5228_LDO12_115 (0x03<<1)
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#define RTS5228_LDO12_120 (0x04<<1)
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#define RTS5228_LDO12_125 (0x05<<1)
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#define RTS5228_LDO12_130 (0x06<<1)
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#define RTS5228_LDO12_135 (0x07<<1)
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#define RTS5228_REG_PWD_LDO12 (0x01<<0)
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#define RTS5228_REG_LDO12_L12 0xFF6F
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#define RTS5228_LDO12_L12_MASK (0x07<<4)
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#define RTS5228_LDO12_L12_120 (0x04<<4)
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/* LDO control register */
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#define RTS5228_CARD_PWR_CTL 0xFD50
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#define RTS5228_PUPDC (0x01<<5)
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#define RTS5228_LDO1233318_POW_CTL 0xFF70
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#define RTS5228_LDO3318_POWERON (0x01<<3)
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#define RTS5228_LDO1_POWEROFF (0x00<<0)
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#define RTS5228_LDO1_SOFTSTART (0x01<<0)
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#define RTS5228_LDO1_FULLON (0x03<<0)
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#define RTS5228_LDO1_POWERON_MASK (0x03<<0)
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#define RTS5228_LDO_POWERON_MASK (0x0F<<0)
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#define RTS5228_DV3318_CFG 0xFF71
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#define RTS5228_DV3318_TUNE_MASK (0x07<<4)
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#define RTS5228_DV3318_17 (0x00<<4)
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#define RTS5228_DV3318_1V75 (0x01<<4)
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#define RTS5228_DV3318_18 (0x02<<4)
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#define RTS5228_DV3318_1V85 (0x03<<4)
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#define RTS5228_DV3318_19 (0x04<<4)
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#define RTS5228_DV3318_33 (0x07<<4)
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#define RTS5228_DV3318_SR_MASK (0x03<<2)
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#define RTS5228_DV3318_SR_0 (0x00<<2)
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#define RTS5228_DV3318_SR_250 (0x01<<2)
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#define RTS5228_DV3318_SR_500 (0x02<<2)
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#define RTS5228_DV3318_SR_1000 (0x03<<2)
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#define RTS5228_LDO1_CFG0 0xFF72
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#define RTS5228_LDO1_OCP_THD_MASK (0x07<<5)
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#define RTS5228_LDO1_OCP_EN (0x01<<4)
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#define RTS5228_LDO1_OCP_LMT_THD_MASK (0x03<<2)
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#define RTS5228_LDO1_OCP_LMT_EN (0x01<<1)
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#define RTS5228_LDO1_OCP_THD_730 (0x00<<5)
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#define RTS5228_LDO1_OCP_THD_780 (0x01<<5)
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#define RTS5228_LDO1_OCP_THD_860 (0x02<<5)
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#define RTS5228_LDO1_OCP_THD_930 (0x03<<5)
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#define RTS5228_LDO1_OCP_THD_1000 (0x04<<5)
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#define RTS5228_LDO1_OCP_THD_1070 (0x05<<5)
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#define RTS5228_LDO1_OCP_THD_1140 (0x06<<5)
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#define RTS5228_LDO1_OCP_THD_1220 (0x07<<5)
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#define RTS5228_LDO1_LMT_THD_450 (0x00<<2)
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#define RTS5228_LDO1_LMT_THD_1000 (0x01<<2)
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#define RTS5228_LDO1_LMT_THD_1500 (0x02<<2)
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#define RTS5228_LDO1_LMT_THD_2000 (0x03<<2)
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#define RTS5228_LDO1_CFG1 0xFF73
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#define RTS5228_LDO1_SR_TIME_MASK (0x03<<6)
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#define RTS5228_LDO1_SR_0_0 (0x00<<6)
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#define RTS5228_LDO1_SR_0_25 (0x01<<6)
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#define RTS5228_LDO1_SR_0_5 (0x02<<6)
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#define RTS5228_LDO1_SR_1_0 (0x03<<6)
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#define RTS5228_LDO1_TUNE_MASK (0x07<<1)
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#define RTS5228_LDO1_18 (0x05<<1)
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#define RTS5228_LDO1_33 (0x07<<1)
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#define RTS5228_LDO1_PWD_MASK (0x01<<0)
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#define RTS5228_AUXCLK_GAT_CTL 0xFF74
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#define RTS5228_REG_RREF_CTL_0 0xFF75
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#define RTS5228_FORCE_RREF_EXTL (0x01<<7)
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#define RTS5228_REG_BG33_MASK (0x07<<0)
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#define RTS5228_RREF_12_1V (0x04<<0)
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#define RTS5228_RREF_12_3V (0x05<<0)
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#define RTS5228_REG_RREF_CTL_1 0xFF76
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#define RTS5228_REG_RREF_CTL_2 0xFF77
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#define RTS5228_TEST_INTL_RREF (0x01<<7)
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#define RTS5228_DGLCH_TIME_MASK (0x03<<5)
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#define RTS5228_DGLCH_TIME_50 (0x00<<5)
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#define RTS5228_DGLCH_TIME_75 (0x01<<5)
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#define RTS5228_DGLCH_TIME_100 (0x02<<5)
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#define RTS5228_DGLCH_TIME_125 (0x03<<5)
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#define RTS5228_REG_REXT_TUNE_MASK (0x1F<<0)
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#define RTS5228_REG_PME_FORCE_CTL 0xFF78
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#define FORCE_PM_CONTROL 0x20
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#define FORCE_PM_VALUE 0x10
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/* Single LUN, support SD */
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#define DEFAULT_SINGLE 0
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#define SD_LUN 1
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/* For Change_FPGA_SSCClock Function */
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#define MULTIPLY_BY_1 0x00
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#define MULTIPLY_BY_2 0x01
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#define MULTIPLY_BY_3 0x02
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#define MULTIPLY_BY_4 0x03
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#define MULTIPLY_BY_5 0x04
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#define MULTIPLY_BY_6 0x05
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#define MULTIPLY_BY_7 0x06
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#define MULTIPLY_BY_8 0x07
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#define MULTIPLY_BY_9 0x08
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#define MULTIPLY_BY_10 0x09
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#define DIVIDE_BY_2 0x01
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#define DIVIDE_BY_3 0x02
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#define DIVIDE_BY_4 0x03
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#define DIVIDE_BY_5 0x04
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#define DIVIDE_BY_6 0x05
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#define DIVIDE_BY_7 0x06
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#define DIVIDE_BY_8 0x07
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#define DIVIDE_BY_9 0x08
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#define DIVIDE_BY_10 0x09
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int rts5228_pci_switch_clock(struct rtsx_pcr *pcr, unsigned int card_clock,
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u8 ssc_depth, bool initial_mode, bool double_clk, bool vpclk);
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#endif /* RTS5228_H */
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