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e9fdf122cf
With the previous commit there is no need for the lowlevel driver any more to specify it it uses two or three cells. So simplify accordingly. The only non-trival change affects the pwm-rockchip driver: It used to only support three cells if the hardware supports polarity. Now the default number depends on the device tree which has to match hardware anyhow (and if it doesn't the error is just a bit delayed as a PWM handle with an inverted setting is catched when pwm_apply_state() is called). Signed-off-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de> Signed-off-by: Thierry Reding <thierry.reding@gmail.com>
280 lines
7.4 KiB
C
280 lines
7.4 KiB
C
/*
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* Copyright (C) 2016 Broadcom
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation version 2.
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*
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* This program is distributed "as is" WITHOUT ANY WARRANTY of any
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* kind, whether express or implied; without even the implied warranty
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* of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#include <linux/clk.h>
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#include <linux/delay.h>
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#include <linux/err.h>
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#include <linux/io.h>
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#include <linux/math64.h>
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#include <linux/module.h>
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#include <linux/of.h>
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#include <linux/platform_device.h>
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#include <linux/pwm.h>
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#define IPROC_PWM_CTRL_OFFSET 0x00
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#define IPROC_PWM_CTRL_TYPE_SHIFT(ch) (15 + (ch))
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#define IPROC_PWM_CTRL_POLARITY_SHIFT(ch) (8 + (ch))
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#define IPROC_PWM_CTRL_EN_SHIFT(ch) (ch)
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#define IPROC_PWM_PERIOD_OFFSET(ch) (0x04 + ((ch) << 3))
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#define IPROC_PWM_PERIOD_MIN 0x02
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#define IPROC_PWM_PERIOD_MAX 0xffff
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#define IPROC_PWM_DUTY_CYCLE_OFFSET(ch) (0x08 + ((ch) << 3))
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#define IPROC_PWM_DUTY_CYCLE_MIN 0x00
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#define IPROC_PWM_DUTY_CYCLE_MAX 0xffff
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#define IPROC_PWM_PRESCALE_OFFSET 0x24
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#define IPROC_PWM_PRESCALE_BITS 0x06
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#define IPROC_PWM_PRESCALE_SHIFT(ch) ((3 - (ch)) * \
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IPROC_PWM_PRESCALE_BITS)
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#define IPROC_PWM_PRESCALE_MASK(ch) (IPROC_PWM_PRESCALE_MAX << \
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IPROC_PWM_PRESCALE_SHIFT(ch))
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#define IPROC_PWM_PRESCALE_MIN 0x00
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#define IPROC_PWM_PRESCALE_MAX 0x3f
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struct iproc_pwmc {
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struct pwm_chip chip;
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void __iomem *base;
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struct clk *clk;
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};
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static inline struct iproc_pwmc *to_iproc_pwmc(struct pwm_chip *chip)
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{
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return container_of(chip, struct iproc_pwmc, chip);
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}
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static void iproc_pwmc_enable(struct iproc_pwmc *ip, unsigned int channel)
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{
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u32 value;
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value = readl(ip->base + IPROC_PWM_CTRL_OFFSET);
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value |= 1 << IPROC_PWM_CTRL_EN_SHIFT(channel);
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writel(value, ip->base + IPROC_PWM_CTRL_OFFSET);
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/* must be a 400 ns delay between clearing and setting enable bit */
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ndelay(400);
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}
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static void iproc_pwmc_disable(struct iproc_pwmc *ip, unsigned int channel)
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{
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u32 value;
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value = readl(ip->base + IPROC_PWM_CTRL_OFFSET);
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value &= ~(1 << IPROC_PWM_CTRL_EN_SHIFT(channel));
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writel(value, ip->base + IPROC_PWM_CTRL_OFFSET);
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/* must be a 400 ns delay between clearing and setting enable bit */
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ndelay(400);
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}
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static void iproc_pwmc_get_state(struct pwm_chip *chip, struct pwm_device *pwm,
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struct pwm_state *state)
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{
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struct iproc_pwmc *ip = to_iproc_pwmc(chip);
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u64 tmp, multi, rate;
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u32 value, prescale;
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value = readl(ip->base + IPROC_PWM_CTRL_OFFSET);
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if (value & BIT(IPROC_PWM_CTRL_EN_SHIFT(pwm->hwpwm)))
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state->enabled = true;
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else
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state->enabled = false;
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if (value & BIT(IPROC_PWM_CTRL_POLARITY_SHIFT(pwm->hwpwm)))
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state->polarity = PWM_POLARITY_NORMAL;
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else
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state->polarity = PWM_POLARITY_INVERSED;
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rate = clk_get_rate(ip->clk);
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if (rate == 0) {
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state->period = 0;
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state->duty_cycle = 0;
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return;
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}
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value = readl(ip->base + IPROC_PWM_PRESCALE_OFFSET);
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prescale = value >> IPROC_PWM_PRESCALE_SHIFT(pwm->hwpwm);
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prescale &= IPROC_PWM_PRESCALE_MAX;
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multi = NSEC_PER_SEC * (prescale + 1);
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value = readl(ip->base + IPROC_PWM_PERIOD_OFFSET(pwm->hwpwm));
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tmp = (value & IPROC_PWM_PERIOD_MAX) * multi;
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state->period = div64_u64(tmp, rate);
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value = readl(ip->base + IPROC_PWM_DUTY_CYCLE_OFFSET(pwm->hwpwm));
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tmp = (value & IPROC_PWM_PERIOD_MAX) * multi;
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state->duty_cycle = div64_u64(tmp, rate);
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}
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static int iproc_pwmc_apply(struct pwm_chip *chip, struct pwm_device *pwm,
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const struct pwm_state *state)
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{
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unsigned long prescale = IPROC_PWM_PRESCALE_MIN;
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struct iproc_pwmc *ip = to_iproc_pwmc(chip);
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u32 value, period, duty;
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u64 rate;
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rate = clk_get_rate(ip->clk);
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/*
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* Find period count, duty count and prescale to suit duty_cycle and
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* period. This is done according to formulas described below:
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*
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* period_ns = 10^9 * (PRESCALE + 1) * PC / PWM_CLK_RATE
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* duty_ns = 10^9 * (PRESCALE + 1) * DC / PWM_CLK_RATE
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*
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* PC = (PWM_CLK_RATE * period_ns) / (10^9 * (PRESCALE + 1))
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* DC = (PWM_CLK_RATE * duty_ns) / (10^9 * (PRESCALE + 1))
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*/
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while (1) {
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u64 value, div;
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div = NSEC_PER_SEC * (prescale + 1);
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value = rate * state->period;
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period = div64_u64(value, div);
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value = rate * state->duty_cycle;
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duty = div64_u64(value, div);
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if (period < IPROC_PWM_PERIOD_MIN)
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return -EINVAL;
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if (period <= IPROC_PWM_PERIOD_MAX &&
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duty <= IPROC_PWM_DUTY_CYCLE_MAX)
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break;
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/* Otherwise, increase prescale and recalculate counts */
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if (++prescale > IPROC_PWM_PRESCALE_MAX)
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return -EINVAL;
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}
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iproc_pwmc_disable(ip, pwm->hwpwm);
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/* Set prescale */
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value = readl(ip->base + IPROC_PWM_PRESCALE_OFFSET);
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value &= ~IPROC_PWM_PRESCALE_MASK(pwm->hwpwm);
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value |= prescale << IPROC_PWM_PRESCALE_SHIFT(pwm->hwpwm);
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writel(value, ip->base + IPROC_PWM_PRESCALE_OFFSET);
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/* set period and duty cycle */
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writel(period, ip->base + IPROC_PWM_PERIOD_OFFSET(pwm->hwpwm));
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writel(duty, ip->base + IPROC_PWM_DUTY_CYCLE_OFFSET(pwm->hwpwm));
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/* set polarity */
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value = readl(ip->base + IPROC_PWM_CTRL_OFFSET);
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if (state->polarity == PWM_POLARITY_NORMAL)
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value |= 1 << IPROC_PWM_CTRL_POLARITY_SHIFT(pwm->hwpwm);
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else
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value &= ~(1 << IPROC_PWM_CTRL_POLARITY_SHIFT(pwm->hwpwm));
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writel(value, ip->base + IPROC_PWM_CTRL_OFFSET);
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if (state->enabled)
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iproc_pwmc_enable(ip, pwm->hwpwm);
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return 0;
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}
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static const struct pwm_ops iproc_pwm_ops = {
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.apply = iproc_pwmc_apply,
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.get_state = iproc_pwmc_get_state,
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.owner = THIS_MODULE,
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};
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static int iproc_pwmc_probe(struct platform_device *pdev)
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{
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struct iproc_pwmc *ip;
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unsigned int i;
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u32 value;
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int ret;
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ip = devm_kzalloc(&pdev->dev, sizeof(*ip), GFP_KERNEL);
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if (!ip)
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return -ENOMEM;
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platform_set_drvdata(pdev, ip);
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ip->chip.dev = &pdev->dev;
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ip->chip.ops = &iproc_pwm_ops;
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ip->chip.npwm = 4;
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ip->base = devm_platform_ioremap_resource(pdev, 0);
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if (IS_ERR(ip->base))
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return PTR_ERR(ip->base);
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ip->clk = devm_clk_get(&pdev->dev, NULL);
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if (IS_ERR(ip->clk)) {
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dev_err(&pdev->dev, "failed to get clock: %ld\n",
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PTR_ERR(ip->clk));
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return PTR_ERR(ip->clk);
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}
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ret = clk_prepare_enable(ip->clk);
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if (ret < 0) {
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dev_err(&pdev->dev, "failed to enable clock: %d\n", ret);
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return ret;
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}
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/* Set full drive and normal polarity for all channels */
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value = readl(ip->base + IPROC_PWM_CTRL_OFFSET);
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for (i = 0; i < ip->chip.npwm; i++) {
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value &= ~(1 << IPROC_PWM_CTRL_TYPE_SHIFT(i));
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value |= 1 << IPROC_PWM_CTRL_POLARITY_SHIFT(i);
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}
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writel(value, ip->base + IPROC_PWM_CTRL_OFFSET);
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ret = pwmchip_add(&ip->chip);
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if (ret < 0) {
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dev_err(&pdev->dev, "failed to add PWM chip: %d\n", ret);
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clk_disable_unprepare(ip->clk);
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}
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return ret;
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}
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static int iproc_pwmc_remove(struct platform_device *pdev)
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{
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struct iproc_pwmc *ip = platform_get_drvdata(pdev);
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pwmchip_remove(&ip->chip);
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clk_disable_unprepare(ip->clk);
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return 0;
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}
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static const struct of_device_id bcm_iproc_pwmc_dt[] = {
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{ .compatible = "brcm,iproc-pwm" },
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{ },
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};
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MODULE_DEVICE_TABLE(of, bcm_iproc_pwmc_dt);
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static struct platform_driver iproc_pwmc_driver = {
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.driver = {
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.name = "bcm-iproc-pwm",
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.of_match_table = bcm_iproc_pwmc_dt,
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},
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.probe = iproc_pwmc_probe,
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.remove = iproc_pwmc_remove,
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};
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module_platform_driver(iproc_pwmc_driver);
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MODULE_AUTHOR("Yendapally Reddy Dhananjaya Reddy <yendapally.reddy@broadcom.com>");
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MODULE_DESCRIPTION("Broadcom iProc PWM driver");
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MODULE_LICENSE("GPL v2");
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