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6f897a1085
Since commit 52eaba4ced
("pwm: atmel: Rework tracking updates pending
in hardware") the driver doesn't make use of mutexes any more, so the
header defining these doesn't need to be included.
Signed-off-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de>
Acked-by: Alexandre Belloni <alexandre.belloni@bootlin.com>
Acked-by: Claudiu Beznea <claudiu.beznea@microchip.com>
Signed-off-by: Thierry Reding <thierry.reding@gmail.com>
537 lines
13 KiB
C
537 lines
13 KiB
C
// SPDX-License-Identifier: GPL-2.0-only
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/*
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* Driver for Atmel Pulse Width Modulation Controller
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*
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* Copyright (C) 2013 Atmel Corporation
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* Bo Shen <voice.shen@atmel.com>
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*
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* Links to reference manuals for the supported PWM chips can be found in
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* Documentation/arm/microchip.rst.
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*
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* Limitations:
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* - Periods start with the inactive level.
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* - Hardware has to be stopped in general to update settings.
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*
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* Software bugs/possible improvements:
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* - When atmel_pwm_apply() is called with state->enabled=false a change in
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* state->polarity isn't honored.
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* - Instead of sleeping to wait for a completed period, the interrupt
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* functionality could be used.
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*/
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#include <linux/clk.h>
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#include <linux/delay.h>
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#include <linux/err.h>
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#include <linux/io.h>
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#include <linux/module.h>
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#include <linux/of.h>
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#include <linux/of_device.h>
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#include <linux/platform_device.h>
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#include <linux/pwm.h>
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#include <linux/slab.h>
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/* The following is global registers for PWM controller */
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#define PWM_ENA 0x04
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#define PWM_DIS 0x08
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#define PWM_SR 0x0C
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#define PWM_ISR 0x1C
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/* Bit field in SR */
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#define PWM_SR_ALL_CH_ON 0x0F
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/* The following register is PWM channel related registers */
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#define PWM_CH_REG_OFFSET 0x200
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#define PWM_CH_REG_SIZE 0x20
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#define PWM_CMR 0x0
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/* Bit field in CMR */
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#define PWM_CMR_CPOL (1 << 9)
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#define PWM_CMR_UPD_CDTY (1 << 10)
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#define PWM_CMR_CPRE_MSK 0xF
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/* The following registers for PWM v1 */
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#define PWMV1_CDTY 0x04
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#define PWMV1_CPRD 0x08
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#define PWMV1_CUPD 0x10
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/* The following registers for PWM v2 */
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#define PWMV2_CDTY 0x04
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#define PWMV2_CDTYUPD 0x08
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#define PWMV2_CPRD 0x0C
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#define PWMV2_CPRDUPD 0x10
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#define PWM_MAX_PRES 10
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struct atmel_pwm_registers {
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u8 period;
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u8 period_upd;
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u8 duty;
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u8 duty_upd;
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};
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struct atmel_pwm_config {
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u32 period_bits;
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};
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struct atmel_pwm_data {
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struct atmel_pwm_registers regs;
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struct atmel_pwm_config cfg;
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};
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struct atmel_pwm_chip {
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struct pwm_chip chip;
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struct clk *clk;
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void __iomem *base;
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const struct atmel_pwm_data *data;
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/*
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* The hardware supports a mechanism to update a channel's duty cycle at
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* the end of the currently running period. When such an update is
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* pending we delay disabling the PWM until the new configuration is
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* active because otherwise pmw_config(duty_cycle=0); pwm_disable();
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* might not result in an inactive output.
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* This bitmask tracks for which channels an update is pending in
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* hardware.
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*/
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u32 update_pending;
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/* Protects .update_pending */
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spinlock_t lock;
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};
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static inline struct atmel_pwm_chip *to_atmel_pwm_chip(struct pwm_chip *chip)
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{
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return container_of(chip, struct atmel_pwm_chip, chip);
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}
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static inline u32 atmel_pwm_readl(struct atmel_pwm_chip *chip,
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unsigned long offset)
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{
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return readl_relaxed(chip->base + offset);
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}
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static inline void atmel_pwm_writel(struct atmel_pwm_chip *chip,
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unsigned long offset, unsigned long val)
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{
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writel_relaxed(val, chip->base + offset);
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}
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static inline u32 atmel_pwm_ch_readl(struct atmel_pwm_chip *chip,
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unsigned int ch, unsigned long offset)
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{
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unsigned long base = PWM_CH_REG_OFFSET + ch * PWM_CH_REG_SIZE;
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return atmel_pwm_readl(chip, base + offset);
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}
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static inline void atmel_pwm_ch_writel(struct atmel_pwm_chip *chip,
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unsigned int ch, unsigned long offset,
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unsigned long val)
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{
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unsigned long base = PWM_CH_REG_OFFSET + ch * PWM_CH_REG_SIZE;
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atmel_pwm_writel(chip, base + offset, val);
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}
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static void atmel_pwm_update_pending(struct atmel_pwm_chip *chip)
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{
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/*
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* Each channel that has its bit in ISR set started a new period since
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* ISR was cleared and so there is no more update pending. Note that
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* reading ISR clears it, so this needs to handle all channels to not
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* loose information.
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*/
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u32 isr = atmel_pwm_readl(chip, PWM_ISR);
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chip->update_pending &= ~isr;
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}
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static void atmel_pwm_set_pending(struct atmel_pwm_chip *chip, unsigned int ch)
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{
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spin_lock(&chip->lock);
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/*
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* Clear pending flags in hardware because otherwise there might still
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* be a stale flag in ISR.
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*/
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atmel_pwm_update_pending(chip);
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chip->update_pending |= (1 << ch);
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spin_unlock(&chip->lock);
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}
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static int atmel_pwm_test_pending(struct atmel_pwm_chip *chip, unsigned int ch)
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{
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int ret = 0;
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spin_lock(&chip->lock);
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if (chip->update_pending & (1 << ch)) {
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atmel_pwm_update_pending(chip);
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if (chip->update_pending & (1 << ch))
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ret = 1;
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}
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spin_unlock(&chip->lock);
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return ret;
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}
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static int atmel_pwm_wait_nonpending(struct atmel_pwm_chip *chip, unsigned int ch)
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{
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unsigned long timeout = jiffies + 2 * HZ;
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int ret;
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while ((ret = atmel_pwm_test_pending(chip, ch)) &&
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time_before(jiffies, timeout))
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usleep_range(10, 100);
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return ret ? -ETIMEDOUT : 0;
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}
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static int atmel_pwm_calculate_cprd_and_pres(struct pwm_chip *chip,
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unsigned long clkrate,
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const struct pwm_state *state,
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unsigned long *cprd, u32 *pres)
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{
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struct atmel_pwm_chip *atmel_pwm = to_atmel_pwm_chip(chip);
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unsigned long long cycles = state->period;
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int shift;
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/* Calculate the period cycles and prescale value */
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cycles *= clkrate;
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do_div(cycles, NSEC_PER_SEC);
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/*
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* The register for the period length is cfg.period_bits bits wide.
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* So for each bit the number of clock cycles is wider divide the input
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* clock frequency by two using pres and shift cprd accordingly.
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*/
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shift = fls(cycles) - atmel_pwm->data->cfg.period_bits;
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if (shift > PWM_MAX_PRES) {
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dev_err(chip->dev, "pres exceeds the maximum value\n");
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return -EINVAL;
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} else if (shift > 0) {
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*pres = shift;
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cycles >>= *pres;
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} else {
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*pres = 0;
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}
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*cprd = cycles;
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return 0;
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}
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static void atmel_pwm_calculate_cdty(const struct pwm_state *state,
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unsigned long clkrate, unsigned long cprd,
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u32 pres, unsigned long *cdty)
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{
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unsigned long long cycles = state->duty_cycle;
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cycles *= clkrate;
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do_div(cycles, NSEC_PER_SEC);
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cycles >>= pres;
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*cdty = cprd - cycles;
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}
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static void atmel_pwm_update_cdty(struct pwm_chip *chip, struct pwm_device *pwm,
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unsigned long cdty)
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{
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struct atmel_pwm_chip *atmel_pwm = to_atmel_pwm_chip(chip);
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u32 val;
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if (atmel_pwm->data->regs.duty_upd ==
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atmel_pwm->data->regs.period_upd) {
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val = atmel_pwm_ch_readl(atmel_pwm, pwm->hwpwm, PWM_CMR);
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val &= ~PWM_CMR_UPD_CDTY;
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atmel_pwm_ch_writel(atmel_pwm, pwm->hwpwm, PWM_CMR, val);
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}
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atmel_pwm_ch_writel(atmel_pwm, pwm->hwpwm,
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atmel_pwm->data->regs.duty_upd, cdty);
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atmel_pwm_set_pending(atmel_pwm, pwm->hwpwm);
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}
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static void atmel_pwm_set_cprd_cdty(struct pwm_chip *chip,
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struct pwm_device *pwm,
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unsigned long cprd, unsigned long cdty)
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{
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struct atmel_pwm_chip *atmel_pwm = to_atmel_pwm_chip(chip);
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atmel_pwm_ch_writel(atmel_pwm, pwm->hwpwm,
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atmel_pwm->data->regs.duty, cdty);
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atmel_pwm_ch_writel(atmel_pwm, pwm->hwpwm,
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atmel_pwm->data->regs.period, cprd);
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}
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static void atmel_pwm_disable(struct pwm_chip *chip, struct pwm_device *pwm,
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bool disable_clk)
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{
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struct atmel_pwm_chip *atmel_pwm = to_atmel_pwm_chip(chip);
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unsigned long timeout = jiffies + 2 * HZ;
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atmel_pwm_wait_nonpending(atmel_pwm, pwm->hwpwm);
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atmel_pwm_writel(atmel_pwm, PWM_DIS, 1 << pwm->hwpwm);
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/*
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* Wait for the PWM channel disable operation to be effective before
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* stopping the clock.
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*/
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timeout = jiffies + 2 * HZ;
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while ((atmel_pwm_readl(atmel_pwm, PWM_SR) & (1 << pwm->hwpwm)) &&
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time_before(jiffies, timeout))
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usleep_range(10, 100);
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if (disable_clk)
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clk_disable(atmel_pwm->clk);
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}
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static int atmel_pwm_apply(struct pwm_chip *chip, struct pwm_device *pwm,
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const struct pwm_state *state)
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{
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struct atmel_pwm_chip *atmel_pwm = to_atmel_pwm_chip(chip);
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struct pwm_state cstate;
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unsigned long cprd, cdty;
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u32 pres, val;
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int ret;
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pwm_get_state(pwm, &cstate);
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if (state->enabled) {
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unsigned long clkrate = clk_get_rate(atmel_pwm->clk);
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if (cstate.enabled &&
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cstate.polarity == state->polarity &&
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cstate.period == state->period) {
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u32 cmr = atmel_pwm_ch_readl(atmel_pwm, pwm->hwpwm, PWM_CMR);
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cprd = atmel_pwm_ch_readl(atmel_pwm, pwm->hwpwm,
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atmel_pwm->data->regs.period);
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pres = cmr & PWM_CMR_CPRE_MSK;
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atmel_pwm_calculate_cdty(state, clkrate, cprd, pres, &cdty);
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atmel_pwm_update_cdty(chip, pwm, cdty);
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return 0;
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}
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ret = atmel_pwm_calculate_cprd_and_pres(chip, clkrate, state, &cprd,
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&pres);
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if (ret) {
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dev_err(chip->dev,
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"failed to calculate cprd and prescaler\n");
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return ret;
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}
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atmel_pwm_calculate_cdty(state, clkrate, cprd, pres, &cdty);
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if (cstate.enabled) {
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atmel_pwm_disable(chip, pwm, false);
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} else {
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ret = clk_enable(atmel_pwm->clk);
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if (ret) {
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dev_err(chip->dev, "failed to enable clock\n");
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return ret;
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}
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}
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/* It is necessary to preserve CPOL, inside CMR */
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val = atmel_pwm_ch_readl(atmel_pwm, pwm->hwpwm, PWM_CMR);
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val = (val & ~PWM_CMR_CPRE_MSK) | (pres & PWM_CMR_CPRE_MSK);
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if (state->polarity == PWM_POLARITY_NORMAL)
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val &= ~PWM_CMR_CPOL;
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else
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val |= PWM_CMR_CPOL;
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atmel_pwm_ch_writel(atmel_pwm, pwm->hwpwm, PWM_CMR, val);
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atmel_pwm_set_cprd_cdty(chip, pwm, cprd, cdty);
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atmel_pwm_writel(atmel_pwm, PWM_ENA, 1 << pwm->hwpwm);
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} else if (cstate.enabled) {
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atmel_pwm_disable(chip, pwm, true);
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}
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return 0;
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}
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static void atmel_pwm_get_state(struct pwm_chip *chip, struct pwm_device *pwm,
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struct pwm_state *state)
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{
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struct atmel_pwm_chip *atmel_pwm = to_atmel_pwm_chip(chip);
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u32 sr, cmr;
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sr = atmel_pwm_readl(atmel_pwm, PWM_SR);
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cmr = atmel_pwm_ch_readl(atmel_pwm, pwm->hwpwm, PWM_CMR);
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if (sr & (1 << pwm->hwpwm)) {
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unsigned long rate = clk_get_rate(atmel_pwm->clk);
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u32 cdty, cprd, pres;
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u64 tmp;
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pres = cmr & PWM_CMR_CPRE_MSK;
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cprd = atmel_pwm_ch_readl(atmel_pwm, pwm->hwpwm,
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atmel_pwm->data->regs.period);
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tmp = (u64)cprd * NSEC_PER_SEC;
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tmp <<= pres;
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state->period = DIV64_U64_ROUND_UP(tmp, rate);
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/* Wait for an updated duty_cycle queued in hardware */
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atmel_pwm_wait_nonpending(atmel_pwm, pwm->hwpwm);
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cdty = atmel_pwm_ch_readl(atmel_pwm, pwm->hwpwm,
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atmel_pwm->data->regs.duty);
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tmp = (u64)(cprd - cdty) * NSEC_PER_SEC;
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tmp <<= pres;
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state->duty_cycle = DIV64_U64_ROUND_UP(tmp, rate);
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state->enabled = true;
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} else {
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state->enabled = false;
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}
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if (cmr & PWM_CMR_CPOL)
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state->polarity = PWM_POLARITY_INVERSED;
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else
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state->polarity = PWM_POLARITY_NORMAL;
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}
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static const struct pwm_ops atmel_pwm_ops = {
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.apply = atmel_pwm_apply,
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.get_state = atmel_pwm_get_state,
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.owner = THIS_MODULE,
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};
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static const struct atmel_pwm_data atmel_sam9rl_pwm_data = {
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.regs = {
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.period = PWMV1_CPRD,
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.period_upd = PWMV1_CUPD,
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.duty = PWMV1_CDTY,
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.duty_upd = PWMV1_CUPD,
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},
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.cfg = {
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/* 16 bits to keep period and duty. */
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.period_bits = 16,
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},
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};
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static const struct atmel_pwm_data atmel_sama5_pwm_data = {
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.regs = {
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.period = PWMV2_CPRD,
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.period_upd = PWMV2_CPRDUPD,
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.duty = PWMV2_CDTY,
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.duty_upd = PWMV2_CDTYUPD,
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},
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.cfg = {
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/* 16 bits to keep period and duty. */
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.period_bits = 16,
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},
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};
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static const struct atmel_pwm_data mchp_sam9x60_pwm_data = {
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.regs = {
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.period = PWMV1_CPRD,
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.period_upd = PWMV1_CUPD,
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.duty = PWMV1_CDTY,
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.duty_upd = PWMV1_CUPD,
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},
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.cfg = {
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/* 32 bits to keep period and duty. */
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.period_bits = 32,
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},
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};
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static const struct of_device_id atmel_pwm_dt_ids[] = {
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{
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.compatible = "atmel,at91sam9rl-pwm",
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.data = &atmel_sam9rl_pwm_data,
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}, {
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.compatible = "atmel,sama5d3-pwm",
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.data = &atmel_sama5_pwm_data,
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}, {
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.compatible = "atmel,sama5d2-pwm",
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.data = &atmel_sama5_pwm_data,
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}, {
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.compatible = "microchip,sam9x60-pwm",
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.data = &mchp_sam9x60_pwm_data,
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}, {
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/* sentinel */
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},
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};
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MODULE_DEVICE_TABLE(of, atmel_pwm_dt_ids);
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static int atmel_pwm_probe(struct platform_device *pdev)
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{
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struct atmel_pwm_chip *atmel_pwm;
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int ret;
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atmel_pwm = devm_kzalloc(&pdev->dev, sizeof(*atmel_pwm), GFP_KERNEL);
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if (!atmel_pwm)
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return -ENOMEM;
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atmel_pwm->data = of_device_get_match_data(&pdev->dev);
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atmel_pwm->update_pending = 0;
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spin_lock_init(&atmel_pwm->lock);
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atmel_pwm->base = devm_platform_ioremap_resource(pdev, 0);
|
|
if (IS_ERR(atmel_pwm->base))
|
|
return PTR_ERR(atmel_pwm->base);
|
|
|
|
atmel_pwm->clk = devm_clk_get(&pdev->dev, NULL);
|
|
if (IS_ERR(atmel_pwm->clk))
|
|
return PTR_ERR(atmel_pwm->clk);
|
|
|
|
ret = clk_prepare(atmel_pwm->clk);
|
|
if (ret) {
|
|
dev_err(&pdev->dev, "failed to prepare PWM clock\n");
|
|
return ret;
|
|
}
|
|
|
|
atmel_pwm->chip.dev = &pdev->dev;
|
|
atmel_pwm->chip.ops = &atmel_pwm_ops;
|
|
atmel_pwm->chip.npwm = 4;
|
|
|
|
ret = pwmchip_add(&atmel_pwm->chip);
|
|
if (ret < 0) {
|
|
dev_err(&pdev->dev, "failed to add PWM chip %d\n", ret);
|
|
goto unprepare_clk;
|
|
}
|
|
|
|
platform_set_drvdata(pdev, atmel_pwm);
|
|
|
|
return ret;
|
|
|
|
unprepare_clk:
|
|
clk_unprepare(atmel_pwm->clk);
|
|
return ret;
|
|
}
|
|
|
|
static int atmel_pwm_remove(struct platform_device *pdev)
|
|
{
|
|
struct atmel_pwm_chip *atmel_pwm = platform_get_drvdata(pdev);
|
|
|
|
pwmchip_remove(&atmel_pwm->chip);
|
|
|
|
clk_unprepare(atmel_pwm->clk);
|
|
|
|
return 0;
|
|
}
|
|
|
|
static struct platform_driver atmel_pwm_driver = {
|
|
.driver = {
|
|
.name = "atmel-pwm",
|
|
.of_match_table = of_match_ptr(atmel_pwm_dt_ids),
|
|
},
|
|
.probe = atmel_pwm_probe,
|
|
.remove = atmel_pwm_remove,
|
|
};
|
|
module_platform_driver(atmel_pwm_driver);
|
|
|
|
MODULE_ALIAS("platform:atmel-pwm");
|
|
MODULE_AUTHOR("Bo Shen <voice.shen@atmel.com>");
|
|
MODULE_DESCRIPTION("Atmel PWM driver");
|
|
MODULE_LICENSE("GPL v2");
|