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31bd548f40
platform_get_resource(pdev, IORESOURCE_IRQ, ..) relies on static allocation of IRQ resources in DT core code, this causes an issue when using hierarchical interrupt domains using "interrupts" property in the node as this bypassed the hierarchical setup and messed up the irq chaining. In preparation for removal of static setup of IRQ resource from DT core code use platform_get_irq_optional(). Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Signed-off-by: Marc Zyngier <maz@kernel.org> Link: https://lore.kernel.org/r/20211216182121.5323-1-prabhakar.mahadev-lad.rj@bp.renesas.com
611 lines
16 KiB
C
611 lines
16 KiB
C
// SPDX-License-Identifier: GPL-2.0
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/*
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* Renesas INTC External IRQ Pin Driver
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*
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* Copyright (C) 2013 Magnus Damm
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*/
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#include <linux/init.h>
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#include <linux/of.h>
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#include <linux/platform_device.h>
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#include <linux/spinlock.h>
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#include <linux/interrupt.h>
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#include <linux/ioport.h>
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#include <linux/io.h>
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#include <linux/irq.h>
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#include <linux/irqdomain.h>
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#include <linux/err.h>
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#include <linux/slab.h>
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#include <linux/module.h>
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#include <linux/of_device.h>
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#include <linux/pm_runtime.h>
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#define INTC_IRQPIN_MAX 8 /* maximum 8 interrupts per driver instance */
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#define INTC_IRQPIN_REG_SENSE 0 /* ICRn */
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#define INTC_IRQPIN_REG_PRIO 1 /* INTPRInn */
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#define INTC_IRQPIN_REG_SOURCE 2 /* INTREQnn */
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#define INTC_IRQPIN_REG_MASK 3 /* INTMSKnn */
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#define INTC_IRQPIN_REG_CLEAR 4 /* INTMSKCLRnn */
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#define INTC_IRQPIN_REG_NR_MANDATORY 5
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#define INTC_IRQPIN_REG_IRLM 5 /* ICR0 with IRLM bit (optional) */
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#define INTC_IRQPIN_REG_NR 6
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/* INTC external IRQ PIN hardware register access:
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*
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* SENSE is read-write 32-bit with 2-bits or 4-bits per IRQ (*)
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* PRIO is read-write 32-bit with 4-bits per IRQ (**)
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* SOURCE is read-only 32-bit or 8-bit with 1-bit per IRQ (***)
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* MASK is write-only 32-bit or 8-bit with 1-bit per IRQ (***)
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* CLEAR is write-only 32-bit or 8-bit with 1-bit per IRQ (***)
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*
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* (*) May be accessed by more than one driver instance - lock needed
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* (**) Read-modify-write access by one driver instance - lock needed
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* (***) Accessed by one driver instance only - no locking needed
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*/
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struct intc_irqpin_iomem {
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void __iomem *iomem;
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unsigned long (*read)(void __iomem *iomem);
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void (*write)(void __iomem *iomem, unsigned long data);
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int width;
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};
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struct intc_irqpin_irq {
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int hw_irq;
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int requested_irq;
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int domain_irq;
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struct intc_irqpin_priv *p;
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};
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struct intc_irqpin_priv {
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struct intc_irqpin_iomem iomem[INTC_IRQPIN_REG_NR];
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struct intc_irqpin_irq irq[INTC_IRQPIN_MAX];
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unsigned int sense_bitfield_width;
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struct platform_device *pdev;
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struct irq_chip irq_chip;
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struct irq_domain *irq_domain;
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atomic_t wakeup_path;
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unsigned shared_irqs:1;
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u8 shared_irq_mask;
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};
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struct intc_irqpin_config {
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int irlm_bit; /* -1 if non-existent */
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};
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static unsigned long intc_irqpin_read32(void __iomem *iomem)
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{
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return ioread32(iomem);
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}
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static unsigned long intc_irqpin_read8(void __iomem *iomem)
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{
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return ioread8(iomem);
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}
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static void intc_irqpin_write32(void __iomem *iomem, unsigned long data)
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{
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iowrite32(data, iomem);
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}
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static void intc_irqpin_write8(void __iomem *iomem, unsigned long data)
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{
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iowrite8(data, iomem);
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}
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static inline unsigned long intc_irqpin_read(struct intc_irqpin_priv *p,
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int reg)
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{
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struct intc_irqpin_iomem *i = &p->iomem[reg];
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return i->read(i->iomem);
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}
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static inline void intc_irqpin_write(struct intc_irqpin_priv *p,
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int reg, unsigned long data)
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{
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struct intc_irqpin_iomem *i = &p->iomem[reg];
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i->write(i->iomem, data);
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}
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static inline unsigned long intc_irqpin_hwirq_mask(struct intc_irqpin_priv *p,
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int reg, int hw_irq)
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{
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return BIT((p->iomem[reg].width - 1) - hw_irq);
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}
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static inline void intc_irqpin_irq_write_hwirq(struct intc_irqpin_priv *p,
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int reg, int hw_irq)
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{
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intc_irqpin_write(p, reg, intc_irqpin_hwirq_mask(p, reg, hw_irq));
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}
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static DEFINE_RAW_SPINLOCK(intc_irqpin_lock); /* only used by slow path */
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static void intc_irqpin_read_modify_write(struct intc_irqpin_priv *p,
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int reg, int shift,
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int width, int value)
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{
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unsigned long flags;
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unsigned long tmp;
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raw_spin_lock_irqsave(&intc_irqpin_lock, flags);
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tmp = intc_irqpin_read(p, reg);
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tmp &= ~(((1 << width) - 1) << shift);
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tmp |= value << shift;
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intc_irqpin_write(p, reg, tmp);
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raw_spin_unlock_irqrestore(&intc_irqpin_lock, flags);
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}
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static void intc_irqpin_mask_unmask_prio(struct intc_irqpin_priv *p,
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int irq, int do_mask)
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{
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/* The PRIO register is assumed to be 32-bit with fixed 4-bit fields. */
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int bitfield_width = 4;
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int shift = 32 - (irq + 1) * bitfield_width;
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intc_irqpin_read_modify_write(p, INTC_IRQPIN_REG_PRIO,
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shift, bitfield_width,
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do_mask ? 0 : (1 << bitfield_width) - 1);
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}
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static int intc_irqpin_set_sense(struct intc_irqpin_priv *p, int irq, int value)
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{
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/* The SENSE register is assumed to be 32-bit. */
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int bitfield_width = p->sense_bitfield_width;
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int shift = 32 - (irq + 1) * bitfield_width;
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dev_dbg(&p->pdev->dev, "sense irq = %d, mode = %d\n", irq, value);
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if (value >= (1 << bitfield_width))
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return -EINVAL;
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intc_irqpin_read_modify_write(p, INTC_IRQPIN_REG_SENSE, shift,
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bitfield_width, value);
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return 0;
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}
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static void intc_irqpin_dbg(struct intc_irqpin_irq *i, char *str)
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{
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dev_dbg(&i->p->pdev->dev, "%s (%d:%d:%d)\n",
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str, i->requested_irq, i->hw_irq, i->domain_irq);
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}
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static void intc_irqpin_irq_enable(struct irq_data *d)
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{
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struct intc_irqpin_priv *p = irq_data_get_irq_chip_data(d);
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int hw_irq = irqd_to_hwirq(d);
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intc_irqpin_dbg(&p->irq[hw_irq], "enable");
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intc_irqpin_irq_write_hwirq(p, INTC_IRQPIN_REG_CLEAR, hw_irq);
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}
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static void intc_irqpin_irq_disable(struct irq_data *d)
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{
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struct intc_irqpin_priv *p = irq_data_get_irq_chip_data(d);
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int hw_irq = irqd_to_hwirq(d);
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intc_irqpin_dbg(&p->irq[hw_irq], "disable");
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intc_irqpin_irq_write_hwirq(p, INTC_IRQPIN_REG_MASK, hw_irq);
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}
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static void intc_irqpin_shared_irq_enable(struct irq_data *d)
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{
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struct intc_irqpin_priv *p = irq_data_get_irq_chip_data(d);
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int hw_irq = irqd_to_hwirq(d);
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intc_irqpin_dbg(&p->irq[hw_irq], "shared enable");
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intc_irqpin_irq_write_hwirq(p, INTC_IRQPIN_REG_CLEAR, hw_irq);
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p->shared_irq_mask &= ~BIT(hw_irq);
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}
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static void intc_irqpin_shared_irq_disable(struct irq_data *d)
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{
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struct intc_irqpin_priv *p = irq_data_get_irq_chip_data(d);
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int hw_irq = irqd_to_hwirq(d);
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intc_irqpin_dbg(&p->irq[hw_irq], "shared disable");
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intc_irqpin_irq_write_hwirq(p, INTC_IRQPIN_REG_MASK, hw_irq);
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p->shared_irq_mask |= BIT(hw_irq);
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}
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static void intc_irqpin_irq_enable_force(struct irq_data *d)
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{
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struct intc_irqpin_priv *p = irq_data_get_irq_chip_data(d);
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int irq = p->irq[irqd_to_hwirq(d)].requested_irq;
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intc_irqpin_irq_enable(d);
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/* enable interrupt through parent interrupt controller,
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* assumes non-shared interrupt with 1:1 mapping
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* needed for busted IRQs on some SoCs like sh73a0
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*/
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irq_get_chip(irq)->irq_unmask(irq_get_irq_data(irq));
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}
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static void intc_irqpin_irq_disable_force(struct irq_data *d)
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{
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struct intc_irqpin_priv *p = irq_data_get_irq_chip_data(d);
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int irq = p->irq[irqd_to_hwirq(d)].requested_irq;
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/* disable interrupt through parent interrupt controller,
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* assumes non-shared interrupt with 1:1 mapping
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* needed for busted IRQs on some SoCs like sh73a0
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*/
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irq_get_chip(irq)->irq_mask(irq_get_irq_data(irq));
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intc_irqpin_irq_disable(d);
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}
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#define INTC_IRQ_SENSE_VALID 0x10
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#define INTC_IRQ_SENSE(x) (x + INTC_IRQ_SENSE_VALID)
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static unsigned char intc_irqpin_sense[IRQ_TYPE_SENSE_MASK + 1] = {
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[IRQ_TYPE_EDGE_FALLING] = INTC_IRQ_SENSE(0x00),
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[IRQ_TYPE_EDGE_RISING] = INTC_IRQ_SENSE(0x01),
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[IRQ_TYPE_LEVEL_LOW] = INTC_IRQ_SENSE(0x02),
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[IRQ_TYPE_LEVEL_HIGH] = INTC_IRQ_SENSE(0x03),
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[IRQ_TYPE_EDGE_BOTH] = INTC_IRQ_SENSE(0x04),
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};
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static int intc_irqpin_irq_set_type(struct irq_data *d, unsigned int type)
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{
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unsigned char value = intc_irqpin_sense[type & IRQ_TYPE_SENSE_MASK];
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struct intc_irqpin_priv *p = irq_data_get_irq_chip_data(d);
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if (!(value & INTC_IRQ_SENSE_VALID))
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return -EINVAL;
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return intc_irqpin_set_sense(p, irqd_to_hwirq(d),
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value ^ INTC_IRQ_SENSE_VALID);
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}
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static int intc_irqpin_irq_set_wake(struct irq_data *d, unsigned int on)
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{
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struct intc_irqpin_priv *p = irq_data_get_irq_chip_data(d);
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int hw_irq = irqd_to_hwirq(d);
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irq_set_irq_wake(p->irq[hw_irq].requested_irq, on);
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if (on)
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atomic_inc(&p->wakeup_path);
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else
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atomic_dec(&p->wakeup_path);
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return 0;
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}
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static irqreturn_t intc_irqpin_irq_handler(int irq, void *dev_id)
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{
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struct intc_irqpin_irq *i = dev_id;
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struct intc_irqpin_priv *p = i->p;
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unsigned long bit;
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intc_irqpin_dbg(i, "demux1");
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bit = intc_irqpin_hwirq_mask(p, INTC_IRQPIN_REG_SOURCE, i->hw_irq);
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if (intc_irqpin_read(p, INTC_IRQPIN_REG_SOURCE) & bit) {
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intc_irqpin_write(p, INTC_IRQPIN_REG_SOURCE, ~bit);
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intc_irqpin_dbg(i, "demux2");
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generic_handle_irq(i->domain_irq);
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return IRQ_HANDLED;
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}
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return IRQ_NONE;
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}
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static irqreturn_t intc_irqpin_shared_irq_handler(int irq, void *dev_id)
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{
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struct intc_irqpin_priv *p = dev_id;
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unsigned int reg_source = intc_irqpin_read(p, INTC_IRQPIN_REG_SOURCE);
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irqreturn_t status = IRQ_NONE;
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int k;
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for (k = 0; k < 8; k++) {
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if (reg_source & BIT(7 - k)) {
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if (BIT(k) & p->shared_irq_mask)
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continue;
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status |= intc_irqpin_irq_handler(irq, &p->irq[k]);
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}
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}
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return status;
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}
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/*
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* This lock class tells lockdep that INTC External IRQ Pin irqs are in a
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* different category than their parents, so it won't report false recursion.
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*/
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static struct lock_class_key intc_irqpin_irq_lock_class;
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/* And this is for the request mutex */
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static struct lock_class_key intc_irqpin_irq_request_class;
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static int intc_irqpin_irq_domain_map(struct irq_domain *h, unsigned int virq,
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irq_hw_number_t hw)
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{
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struct intc_irqpin_priv *p = h->host_data;
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p->irq[hw].domain_irq = virq;
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p->irq[hw].hw_irq = hw;
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intc_irqpin_dbg(&p->irq[hw], "map");
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irq_set_chip_data(virq, h->host_data);
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irq_set_lockdep_class(virq, &intc_irqpin_irq_lock_class,
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&intc_irqpin_irq_request_class);
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irq_set_chip_and_handler(virq, &p->irq_chip, handle_level_irq);
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return 0;
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}
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static const struct irq_domain_ops intc_irqpin_irq_domain_ops = {
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.map = intc_irqpin_irq_domain_map,
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.xlate = irq_domain_xlate_twocell,
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};
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static const struct intc_irqpin_config intc_irqpin_irlm_r8a777x = {
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.irlm_bit = 23, /* ICR0.IRLM0 */
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};
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static const struct intc_irqpin_config intc_irqpin_rmobile = {
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.irlm_bit = -1,
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};
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static const struct of_device_id intc_irqpin_dt_ids[] = {
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{ .compatible = "renesas,intc-irqpin", },
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{ .compatible = "renesas,intc-irqpin-r8a7778",
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.data = &intc_irqpin_irlm_r8a777x },
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{ .compatible = "renesas,intc-irqpin-r8a7779",
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.data = &intc_irqpin_irlm_r8a777x },
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{ .compatible = "renesas,intc-irqpin-r8a7740",
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.data = &intc_irqpin_rmobile },
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{ .compatible = "renesas,intc-irqpin-sh73a0",
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.data = &intc_irqpin_rmobile },
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{},
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};
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MODULE_DEVICE_TABLE(of, intc_irqpin_dt_ids);
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static int intc_irqpin_probe(struct platform_device *pdev)
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{
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const struct intc_irqpin_config *config;
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struct device *dev = &pdev->dev;
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struct intc_irqpin_priv *p;
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struct intc_irqpin_iomem *i;
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struct resource *io[INTC_IRQPIN_REG_NR];
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struct irq_chip *irq_chip;
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void (*enable_fn)(struct irq_data *d);
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void (*disable_fn)(struct irq_data *d);
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const char *name = dev_name(dev);
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bool control_parent;
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unsigned int nirqs;
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int ref_irq;
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int ret;
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int k;
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p = devm_kzalloc(dev, sizeof(*p), GFP_KERNEL);
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if (!p)
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return -ENOMEM;
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/* deal with driver instance configuration */
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of_property_read_u32(dev->of_node, "sense-bitfield-width",
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&p->sense_bitfield_width);
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control_parent = of_property_read_bool(dev->of_node, "control-parent");
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if (!p->sense_bitfield_width)
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p->sense_bitfield_width = 4; /* default to 4 bits */
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p->pdev = pdev;
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platform_set_drvdata(pdev, p);
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config = of_device_get_match_data(dev);
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pm_runtime_enable(dev);
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pm_runtime_get_sync(dev);
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/* get hold of register banks */
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memset(io, 0, sizeof(io));
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for (k = 0; k < INTC_IRQPIN_REG_NR; k++) {
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io[k] = platform_get_resource(pdev, IORESOURCE_MEM, k);
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if (!io[k] && k < INTC_IRQPIN_REG_NR_MANDATORY) {
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dev_err(dev, "not enough IOMEM resources\n");
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ret = -EINVAL;
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goto err0;
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}
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}
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/* allow any number of IRQs between 1 and INTC_IRQPIN_MAX */
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for (k = 0; k < INTC_IRQPIN_MAX; k++) {
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ret = platform_get_irq_optional(pdev, k);
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if (ret == -ENXIO)
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break;
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if (ret < 0)
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goto err0;
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p->irq[k].p = p;
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p->irq[k].requested_irq = ret;
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}
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nirqs = k;
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if (nirqs < 1) {
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dev_err(dev, "not enough IRQ resources\n");
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ret = -EINVAL;
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goto err0;
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}
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/* ioremap IOMEM and setup read/write callbacks */
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for (k = 0; k < INTC_IRQPIN_REG_NR; k++) {
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i = &p->iomem[k];
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/* handle optional registers */
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if (!io[k])
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continue;
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switch (resource_size(io[k])) {
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case 1:
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i->width = 8;
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i->read = intc_irqpin_read8;
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i->write = intc_irqpin_write8;
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break;
|
|
case 4:
|
|
i->width = 32;
|
|
i->read = intc_irqpin_read32;
|
|
i->write = intc_irqpin_write32;
|
|
break;
|
|
default:
|
|
dev_err(dev, "IOMEM size mismatch\n");
|
|
ret = -EINVAL;
|
|
goto err0;
|
|
}
|
|
|
|
i->iomem = devm_ioremap(dev, io[k]->start,
|
|
resource_size(io[k]));
|
|
if (!i->iomem) {
|
|
dev_err(dev, "failed to remap IOMEM\n");
|
|
ret = -ENXIO;
|
|
goto err0;
|
|
}
|
|
}
|
|
|
|
/* configure "individual IRQ mode" where needed */
|
|
if (config && config->irlm_bit >= 0) {
|
|
if (io[INTC_IRQPIN_REG_IRLM])
|
|
intc_irqpin_read_modify_write(p, INTC_IRQPIN_REG_IRLM,
|
|
config->irlm_bit, 1, 1);
|
|
else
|
|
dev_warn(dev, "unable to select IRLM mode\n");
|
|
}
|
|
|
|
/* mask all interrupts using priority */
|
|
for (k = 0; k < nirqs; k++)
|
|
intc_irqpin_mask_unmask_prio(p, k, 1);
|
|
|
|
/* clear all pending interrupts */
|
|
intc_irqpin_write(p, INTC_IRQPIN_REG_SOURCE, 0x0);
|
|
|
|
/* scan for shared interrupt lines */
|
|
ref_irq = p->irq[0].requested_irq;
|
|
p->shared_irqs = 1;
|
|
for (k = 1; k < nirqs; k++) {
|
|
if (ref_irq != p->irq[k].requested_irq) {
|
|
p->shared_irqs = 0;
|
|
break;
|
|
}
|
|
}
|
|
|
|
/* use more severe masking method if requested */
|
|
if (control_parent) {
|
|
enable_fn = intc_irqpin_irq_enable_force;
|
|
disable_fn = intc_irqpin_irq_disable_force;
|
|
} else if (!p->shared_irqs) {
|
|
enable_fn = intc_irqpin_irq_enable;
|
|
disable_fn = intc_irqpin_irq_disable;
|
|
} else {
|
|
enable_fn = intc_irqpin_shared_irq_enable;
|
|
disable_fn = intc_irqpin_shared_irq_disable;
|
|
}
|
|
|
|
irq_chip = &p->irq_chip;
|
|
irq_chip->name = "intc-irqpin";
|
|
irq_chip->parent_device = dev;
|
|
irq_chip->irq_mask = disable_fn;
|
|
irq_chip->irq_unmask = enable_fn;
|
|
irq_chip->irq_set_type = intc_irqpin_irq_set_type;
|
|
irq_chip->irq_set_wake = intc_irqpin_irq_set_wake;
|
|
irq_chip->flags = IRQCHIP_MASK_ON_SUSPEND;
|
|
|
|
p->irq_domain = irq_domain_add_simple(dev->of_node, nirqs, 0,
|
|
&intc_irqpin_irq_domain_ops, p);
|
|
if (!p->irq_domain) {
|
|
ret = -ENXIO;
|
|
dev_err(dev, "cannot initialize irq domain\n");
|
|
goto err0;
|
|
}
|
|
|
|
if (p->shared_irqs) {
|
|
/* request one shared interrupt */
|
|
if (devm_request_irq(dev, p->irq[0].requested_irq,
|
|
intc_irqpin_shared_irq_handler,
|
|
IRQF_SHARED, name, p)) {
|
|
dev_err(dev, "failed to request low IRQ\n");
|
|
ret = -ENOENT;
|
|
goto err1;
|
|
}
|
|
} else {
|
|
/* request interrupts one by one */
|
|
for (k = 0; k < nirqs; k++) {
|
|
if (devm_request_irq(dev, p->irq[k].requested_irq,
|
|
intc_irqpin_irq_handler, 0, name,
|
|
&p->irq[k])) {
|
|
dev_err(dev, "failed to request low IRQ\n");
|
|
ret = -ENOENT;
|
|
goto err1;
|
|
}
|
|
}
|
|
}
|
|
|
|
/* unmask all interrupts on prio level */
|
|
for (k = 0; k < nirqs; k++)
|
|
intc_irqpin_mask_unmask_prio(p, k, 0);
|
|
|
|
dev_info(dev, "driving %d irqs\n", nirqs);
|
|
|
|
return 0;
|
|
|
|
err1:
|
|
irq_domain_remove(p->irq_domain);
|
|
err0:
|
|
pm_runtime_put(dev);
|
|
pm_runtime_disable(dev);
|
|
return ret;
|
|
}
|
|
|
|
static int intc_irqpin_remove(struct platform_device *pdev)
|
|
{
|
|
struct intc_irqpin_priv *p = platform_get_drvdata(pdev);
|
|
|
|
irq_domain_remove(p->irq_domain);
|
|
pm_runtime_put(&pdev->dev);
|
|
pm_runtime_disable(&pdev->dev);
|
|
return 0;
|
|
}
|
|
|
|
static int __maybe_unused intc_irqpin_suspend(struct device *dev)
|
|
{
|
|
struct intc_irqpin_priv *p = dev_get_drvdata(dev);
|
|
|
|
if (atomic_read(&p->wakeup_path))
|
|
device_set_wakeup_path(dev);
|
|
|
|
return 0;
|
|
}
|
|
|
|
static SIMPLE_DEV_PM_OPS(intc_irqpin_pm_ops, intc_irqpin_suspend, NULL);
|
|
|
|
static struct platform_driver intc_irqpin_device_driver = {
|
|
.probe = intc_irqpin_probe,
|
|
.remove = intc_irqpin_remove,
|
|
.driver = {
|
|
.name = "renesas_intc_irqpin",
|
|
.of_match_table = intc_irqpin_dt_ids,
|
|
.pm = &intc_irqpin_pm_ops,
|
|
}
|
|
};
|
|
|
|
static int __init intc_irqpin_init(void)
|
|
{
|
|
return platform_driver_register(&intc_irqpin_device_driver);
|
|
}
|
|
postcore_initcall(intc_irqpin_init);
|
|
|
|
static void __exit intc_irqpin_exit(void)
|
|
{
|
|
platform_driver_unregister(&intc_irqpin_device_driver);
|
|
}
|
|
module_exit(intc_irqpin_exit);
|
|
|
|
MODULE_AUTHOR("Magnus Damm");
|
|
MODULE_DESCRIPTION("Renesas INTC External IRQ Pin Driver");
|
|
MODULE_LICENSE("GPL v2");
|