Suzuki K Poulose 314d53d297 arm64: Handle mismatched cache type ... Track mismatches in the cache type register (CTR_EL0), other than the D/I min line sizes and trap user accesses if there are any. Fixes: be68a8aaf9 ("arm64: cpufeature: Fix CTR_EL0 field definitions") Cc: <stable@vger.kernel.org> Cc: Mark Rutland <mark.rutland@arm.com> Cc: Will Deacon <will.deacon@arm.com> Cc: Catalin Marinas <catalin.marinas@arm.com> Signed-off-by: Suzuki K Poulose <suzuki.poulose@arm.com> Signed-off-by: Will Deacon <will.deacon@arm.com>		2018-07-05 10:20:59 +01:00
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asm	arm64: Handle mismatched cache type	2018-07-05 10:20:59 +01:00
uapi/asm	Small update for KVM.	2018-06-12 11:34:04 -07:00