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On HiSilicon Hip09 platform, there are 4 UC (unified cache) modules on each chip CCL (CPU Cluster). UC is a cache that provides coherence between NUMA and UMA domains. It is located between L2 and Memory System. Many PMU events are supported. Let's support the UC PMU driver using the HiSilicon uncore PMU framework. * rd_req_en : rd_req_en is the abbreviation of read request tracetag enable and allows user to count only read operations. Details are listed in the hisi-pmu document at Documentation/admin-guide/perf/hisi-pmu.rst * srcid_en & srcid: Allows users to filter statistical information based on specific CPU/ICL by srcid. srcid_en depends on rd_req_en being enabled. * uring_channel: Allows users to filter statistical information based on the specified tx request uring channel. uring_channel only supported events: [0x47 ~ 0x59]. Signed-off-by: Junhao He <hejunhao3@huawei.com> Reviewed-by: Yicong Yang <yangyicong@hisilicon.com> Reviewed-by: Jonathan Cameron <Jonathan.Cameron@huawei.com> Acked-by: Mark Rutland <mark.rutland@arm.com> Link: https://lore.kernel.org/r/20230615125926.29832-3-hejunhao3@huawei.com Signed-off-by: Will Deacon <will@kernel.org> |
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| .. | ||
| amlogic | ||
| arm_cspmu | ||
| hisilicon | ||
| alibaba_uncore_drw_pmu.c | ||
| apple_m1_cpu_pmu.c | ||
| arm_dmc620_pmu.c | ||
| arm_dsu_pmu.c | ||
| arm_pmu_acpi.c | ||
| arm_pmu_platform.c | ||
| arm_pmu.c | ||
| arm_pmuv3.c | ||
| arm_smmuv3_pmu.c | ||
| arm_spe_pmu.c | ||
| arm-cci.c | ||
| arm-ccn.c | ||
| arm-cmn.c | ||
| fsl_imx8_ddr_perf.c | ||
| fsl_imx9_ddr_perf.c | ||
| Kconfig | ||
| Makefile | ||
| marvell_cn10k_ddr_pmu.c | ||
| marvell_cn10k_tad_pmu.c | ||
| qcom_l2_pmu.c | ||
| qcom_l3_pmu.c | ||
| riscv_pmu_legacy.c | ||
| riscv_pmu_sbi.c | ||
| riscv_pmu.c | ||
| thunderx2_pmu.c | ||
| xgene_pmu.c | ||