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30f3984ede
Add new pci id. Reviewed-by: Rex Zhu <Rex.Zhu@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com> Cc: stable@vger.kernel.org
481 lines
14 KiB
C
481 lines
14 KiB
C
/*
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* Copyright 2015 Advanced Micro Devices, Inc.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
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* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
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* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
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* OTHER DEALINGS IN THE SOFTWARE.
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*
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*
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*/
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#include <linux/list.h>
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#include <linux/slab.h>
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#include <drm/drmP.h>
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#include <linux/firmware.h>
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#include <drm/amdgpu_drm.h>
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#include "amdgpu.h"
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#include "atom.h"
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#include "amdgpu_ucode.h"
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struct amdgpu_cgs_device {
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struct cgs_device base;
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struct amdgpu_device *adev;
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};
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#define CGS_FUNC_ADEV \
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struct amdgpu_device *adev = \
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((struct amdgpu_cgs_device *)cgs_device)->adev
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static uint32_t amdgpu_cgs_read_register(struct cgs_device *cgs_device, unsigned offset)
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{
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CGS_FUNC_ADEV;
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return RREG32(offset);
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}
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static void amdgpu_cgs_write_register(struct cgs_device *cgs_device, unsigned offset,
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uint32_t value)
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{
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CGS_FUNC_ADEV;
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WREG32(offset, value);
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}
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static uint32_t amdgpu_cgs_read_ind_register(struct cgs_device *cgs_device,
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enum cgs_ind_reg space,
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unsigned index)
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{
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CGS_FUNC_ADEV;
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switch (space) {
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case CGS_IND_REG__MMIO:
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return RREG32_IDX(index);
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case CGS_IND_REG__PCIE:
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return RREG32_PCIE(index);
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case CGS_IND_REG__SMC:
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return RREG32_SMC(index);
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case CGS_IND_REG__UVD_CTX:
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return RREG32_UVD_CTX(index);
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case CGS_IND_REG__DIDT:
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return RREG32_DIDT(index);
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case CGS_IND_REG_GC_CAC:
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return RREG32_GC_CAC(index);
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case CGS_IND_REG_SE_CAC:
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return RREG32_SE_CAC(index);
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case CGS_IND_REG__AUDIO_ENDPT:
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DRM_ERROR("audio endpt register access not implemented.\n");
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return 0;
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}
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WARN(1, "Invalid indirect register space");
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return 0;
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}
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static void amdgpu_cgs_write_ind_register(struct cgs_device *cgs_device,
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enum cgs_ind_reg space,
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unsigned index, uint32_t value)
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{
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CGS_FUNC_ADEV;
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switch (space) {
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case CGS_IND_REG__MMIO:
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return WREG32_IDX(index, value);
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case CGS_IND_REG__PCIE:
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return WREG32_PCIE(index, value);
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case CGS_IND_REG__SMC:
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return WREG32_SMC(index, value);
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case CGS_IND_REG__UVD_CTX:
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return WREG32_UVD_CTX(index, value);
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case CGS_IND_REG__DIDT:
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return WREG32_DIDT(index, value);
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case CGS_IND_REG_GC_CAC:
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return WREG32_GC_CAC(index, value);
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case CGS_IND_REG_SE_CAC:
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return WREG32_SE_CAC(index, value);
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case CGS_IND_REG__AUDIO_ENDPT:
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DRM_ERROR("audio endpt register access not implemented.\n");
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return;
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}
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WARN(1, "Invalid indirect register space");
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}
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static uint32_t fw_type_convert(struct cgs_device *cgs_device, uint32_t fw_type)
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{
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CGS_FUNC_ADEV;
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enum AMDGPU_UCODE_ID result = AMDGPU_UCODE_ID_MAXIMUM;
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switch (fw_type) {
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case CGS_UCODE_ID_SDMA0:
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result = AMDGPU_UCODE_ID_SDMA0;
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break;
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case CGS_UCODE_ID_SDMA1:
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result = AMDGPU_UCODE_ID_SDMA1;
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break;
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case CGS_UCODE_ID_CP_CE:
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result = AMDGPU_UCODE_ID_CP_CE;
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break;
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case CGS_UCODE_ID_CP_PFP:
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result = AMDGPU_UCODE_ID_CP_PFP;
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break;
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case CGS_UCODE_ID_CP_ME:
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result = AMDGPU_UCODE_ID_CP_ME;
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break;
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case CGS_UCODE_ID_CP_MEC:
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case CGS_UCODE_ID_CP_MEC_JT1:
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result = AMDGPU_UCODE_ID_CP_MEC1;
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break;
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case CGS_UCODE_ID_CP_MEC_JT2:
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/* for VI. JT2 should be the same as JT1, because:
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1, MEC2 and MEC1 use exactly same FW.
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2, JT2 is not pached but JT1 is.
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*/
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if (adev->asic_type >= CHIP_TOPAZ)
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result = AMDGPU_UCODE_ID_CP_MEC1;
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else
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result = AMDGPU_UCODE_ID_CP_MEC2;
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break;
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case CGS_UCODE_ID_RLC_G:
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result = AMDGPU_UCODE_ID_RLC_G;
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break;
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case CGS_UCODE_ID_STORAGE:
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result = AMDGPU_UCODE_ID_STORAGE;
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break;
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default:
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DRM_ERROR("Firmware type not supported\n");
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}
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return result;
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}
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static uint16_t amdgpu_get_firmware_version(struct cgs_device *cgs_device,
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enum cgs_ucode_id type)
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{
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CGS_FUNC_ADEV;
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uint16_t fw_version = 0;
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switch (type) {
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case CGS_UCODE_ID_SDMA0:
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fw_version = adev->sdma.instance[0].fw_version;
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break;
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case CGS_UCODE_ID_SDMA1:
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fw_version = adev->sdma.instance[1].fw_version;
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break;
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case CGS_UCODE_ID_CP_CE:
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fw_version = adev->gfx.ce_fw_version;
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break;
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case CGS_UCODE_ID_CP_PFP:
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fw_version = adev->gfx.pfp_fw_version;
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break;
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case CGS_UCODE_ID_CP_ME:
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fw_version = adev->gfx.me_fw_version;
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break;
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case CGS_UCODE_ID_CP_MEC:
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fw_version = adev->gfx.mec_fw_version;
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break;
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case CGS_UCODE_ID_CP_MEC_JT1:
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fw_version = adev->gfx.mec_fw_version;
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break;
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case CGS_UCODE_ID_CP_MEC_JT2:
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fw_version = adev->gfx.mec_fw_version;
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break;
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case CGS_UCODE_ID_RLC_G:
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fw_version = adev->gfx.rlc_fw_version;
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break;
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case CGS_UCODE_ID_STORAGE:
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break;
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default:
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DRM_ERROR("firmware type %d do not have version\n", type);
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break;
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}
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return fw_version;
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}
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static int amdgpu_cgs_get_firmware_info(struct cgs_device *cgs_device,
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enum cgs_ucode_id type,
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struct cgs_firmware_info *info)
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{
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CGS_FUNC_ADEV;
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if ((CGS_UCODE_ID_SMU != type) && (CGS_UCODE_ID_SMU_SK != type)) {
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uint64_t gpu_addr;
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uint32_t data_size;
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const struct gfx_firmware_header_v1_0 *header;
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enum AMDGPU_UCODE_ID id;
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struct amdgpu_firmware_info *ucode;
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id = fw_type_convert(cgs_device, type);
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ucode = &adev->firmware.ucode[id];
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if (ucode->fw == NULL)
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return -EINVAL;
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gpu_addr = ucode->mc_addr;
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header = (const struct gfx_firmware_header_v1_0 *)ucode->fw->data;
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data_size = le32_to_cpu(header->header.ucode_size_bytes);
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if ((type == CGS_UCODE_ID_CP_MEC_JT1) ||
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(type == CGS_UCODE_ID_CP_MEC_JT2)) {
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gpu_addr += ALIGN(le32_to_cpu(header->header.ucode_size_bytes), PAGE_SIZE);
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data_size = le32_to_cpu(header->jt_size) << 2;
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}
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info->kptr = ucode->kaddr;
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info->image_size = data_size;
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info->mc_addr = gpu_addr;
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info->version = (uint16_t)le32_to_cpu(header->header.ucode_version);
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if (CGS_UCODE_ID_CP_MEC == type)
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info->image_size = le32_to_cpu(header->jt_offset) << 2;
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info->fw_version = amdgpu_get_firmware_version(cgs_device, type);
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info->feature_version = (uint16_t)le32_to_cpu(header->ucode_feature_version);
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} else {
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char fw_name[30] = {0};
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int err = 0;
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uint32_t ucode_size;
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uint32_t ucode_start_address;
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const uint8_t *src;
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const struct smc_firmware_header_v1_0 *hdr;
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const struct common_firmware_header *header;
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struct amdgpu_firmware_info *ucode = NULL;
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if (!adev->pm.fw) {
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switch (adev->asic_type) {
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case CHIP_TAHITI:
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strcpy(fw_name, "radeon/tahiti_smc.bin");
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break;
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case CHIP_PITCAIRN:
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if ((adev->pdev->revision == 0x81) &&
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((adev->pdev->device == 0x6810) ||
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(adev->pdev->device == 0x6811))) {
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info->is_kicker = true;
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strcpy(fw_name, "radeon/pitcairn_k_smc.bin");
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} else {
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strcpy(fw_name, "radeon/pitcairn_smc.bin");
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}
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break;
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case CHIP_VERDE:
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if (((adev->pdev->device == 0x6820) &&
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((adev->pdev->revision == 0x81) ||
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(adev->pdev->revision == 0x83))) ||
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((adev->pdev->device == 0x6821) &&
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((adev->pdev->revision == 0x83) ||
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(adev->pdev->revision == 0x87))) ||
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((adev->pdev->revision == 0x87) &&
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((adev->pdev->device == 0x6823) ||
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(adev->pdev->device == 0x682b)))) {
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info->is_kicker = true;
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strcpy(fw_name, "radeon/verde_k_smc.bin");
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} else {
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strcpy(fw_name, "radeon/verde_smc.bin");
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}
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break;
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case CHIP_OLAND:
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if (((adev->pdev->revision == 0x81) &&
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((adev->pdev->device == 0x6600) ||
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(adev->pdev->device == 0x6604) ||
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(adev->pdev->device == 0x6605) ||
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(adev->pdev->device == 0x6610))) ||
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((adev->pdev->revision == 0x83) &&
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(adev->pdev->device == 0x6610))) {
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info->is_kicker = true;
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strcpy(fw_name, "radeon/oland_k_smc.bin");
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} else {
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strcpy(fw_name, "radeon/oland_smc.bin");
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}
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break;
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case CHIP_HAINAN:
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if (((adev->pdev->revision == 0x81) &&
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(adev->pdev->device == 0x6660)) ||
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((adev->pdev->revision == 0x83) &&
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((adev->pdev->device == 0x6660) ||
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(adev->pdev->device == 0x6663) ||
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(adev->pdev->device == 0x6665) ||
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(adev->pdev->device == 0x6667)))) {
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info->is_kicker = true;
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strcpy(fw_name, "radeon/hainan_k_smc.bin");
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} else if ((adev->pdev->revision == 0xc3) &&
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(adev->pdev->device == 0x6665)) {
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info->is_kicker = true;
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strcpy(fw_name, "radeon/banks_k_2_smc.bin");
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} else {
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strcpy(fw_name, "radeon/hainan_smc.bin");
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}
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break;
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case CHIP_BONAIRE:
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if ((adev->pdev->revision == 0x80) ||
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(adev->pdev->revision == 0x81) ||
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(adev->pdev->device == 0x665f)) {
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info->is_kicker = true;
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strcpy(fw_name, "amdgpu/bonaire_k_smc.bin");
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} else {
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strcpy(fw_name, "amdgpu/bonaire_smc.bin");
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}
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break;
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case CHIP_HAWAII:
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if (adev->pdev->revision == 0x80) {
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info->is_kicker = true;
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strcpy(fw_name, "amdgpu/hawaii_k_smc.bin");
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} else {
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strcpy(fw_name, "amdgpu/hawaii_smc.bin");
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}
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break;
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case CHIP_TOPAZ:
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if (((adev->pdev->device == 0x6900) && (adev->pdev->revision == 0x81)) ||
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((adev->pdev->device == 0x6900) && (adev->pdev->revision == 0x83)) ||
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((adev->pdev->device == 0x6907) && (adev->pdev->revision == 0x87))) {
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info->is_kicker = true;
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strcpy(fw_name, "amdgpu/topaz_k_smc.bin");
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} else
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strcpy(fw_name, "amdgpu/topaz_smc.bin");
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break;
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case CHIP_TONGA:
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if (((adev->pdev->device == 0x6939) && (adev->pdev->revision == 0xf1)) ||
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((adev->pdev->device == 0x6938) && (adev->pdev->revision == 0xf1))) {
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info->is_kicker = true;
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strcpy(fw_name, "amdgpu/tonga_k_smc.bin");
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} else
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strcpy(fw_name, "amdgpu/tonga_smc.bin");
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break;
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case CHIP_FIJI:
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strcpy(fw_name, "amdgpu/fiji_smc.bin");
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break;
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case CHIP_POLARIS11:
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if (type == CGS_UCODE_ID_SMU) {
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if (((adev->pdev->device == 0x67ef) &&
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((adev->pdev->revision == 0xe0) ||
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(adev->pdev->revision == 0xe2) ||
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(adev->pdev->revision == 0xe5))) ||
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((adev->pdev->device == 0x67ff) &&
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((adev->pdev->revision == 0xcf) ||
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(adev->pdev->revision == 0xef) ||
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(adev->pdev->revision == 0xff)))) {
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info->is_kicker = true;
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strcpy(fw_name, "amdgpu/polaris11_k_smc.bin");
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} else
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strcpy(fw_name, "amdgpu/polaris11_smc.bin");
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} else if (type == CGS_UCODE_ID_SMU_SK) {
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strcpy(fw_name, "amdgpu/polaris11_smc_sk.bin");
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}
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break;
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case CHIP_POLARIS10:
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if (type == CGS_UCODE_ID_SMU) {
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if (((adev->pdev->device == 0x67df) &&
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((adev->pdev->revision == 0xe0) ||
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(adev->pdev->revision == 0xe3) ||
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(adev->pdev->revision == 0xe4) ||
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(adev->pdev->revision == 0xe5) ||
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(adev->pdev->revision == 0xe7) ||
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(adev->pdev->revision == 0xef))) ||
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((adev->pdev->device == 0x6fdf) &&
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(adev->pdev->revision == 0xef))) {
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info->is_kicker = true;
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strcpy(fw_name, "amdgpu/polaris10_k_smc.bin");
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} else
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strcpy(fw_name, "amdgpu/polaris10_smc.bin");
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} else if (type == CGS_UCODE_ID_SMU_SK) {
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strcpy(fw_name, "amdgpu/polaris10_smc_sk.bin");
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}
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break;
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case CHIP_POLARIS12:
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strcpy(fw_name, "amdgpu/polaris12_smc.bin");
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break;
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case CHIP_VEGAM:
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strcpy(fw_name, "amdgpu/vegam_smc.bin");
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break;
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case CHIP_VEGA10:
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if ((adev->pdev->device == 0x687f) &&
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((adev->pdev->revision == 0xc0) ||
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(adev->pdev->revision == 0xc1) ||
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(adev->pdev->revision == 0xc3)))
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strcpy(fw_name, "amdgpu/vega10_acg_smc.bin");
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else
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strcpy(fw_name, "amdgpu/vega10_smc.bin");
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break;
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case CHIP_VEGA12:
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strcpy(fw_name, "amdgpu/vega12_smc.bin");
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break;
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case CHIP_VEGA20:
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strcpy(fw_name, "amdgpu/vega20_smc.bin");
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break;
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default:
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DRM_ERROR("SMC firmware not supported\n");
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return -EINVAL;
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}
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err = request_firmware(&adev->pm.fw, fw_name, adev->dev);
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if (err) {
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DRM_ERROR("Failed to request firmware\n");
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return err;
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}
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err = amdgpu_ucode_validate(adev->pm.fw);
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if (err) {
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DRM_ERROR("Failed to load firmware \"%s\"", fw_name);
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release_firmware(adev->pm.fw);
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adev->pm.fw = NULL;
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return err;
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}
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if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) {
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ucode = &adev->firmware.ucode[AMDGPU_UCODE_ID_SMC];
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ucode->ucode_id = AMDGPU_UCODE_ID_SMC;
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ucode->fw = adev->pm.fw;
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header = (const struct common_firmware_header *)ucode->fw->data;
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adev->firmware.fw_size +=
|
|
ALIGN(le32_to_cpu(header->ucode_size_bytes), PAGE_SIZE);
|
|
}
|
|
}
|
|
|
|
hdr = (const struct smc_firmware_header_v1_0 *) adev->pm.fw->data;
|
|
amdgpu_ucode_print_smc_hdr(&hdr->header);
|
|
adev->pm.fw_version = le32_to_cpu(hdr->header.ucode_version);
|
|
ucode_size = le32_to_cpu(hdr->header.ucode_size_bytes);
|
|
ucode_start_address = le32_to_cpu(hdr->ucode_start_addr);
|
|
src = (const uint8_t *)(adev->pm.fw->data +
|
|
le32_to_cpu(hdr->header.ucode_array_offset_bytes));
|
|
|
|
info->version = adev->pm.fw_version;
|
|
info->image_size = ucode_size;
|
|
info->ucode_start_address = ucode_start_address;
|
|
info->kptr = (void *)src;
|
|
}
|
|
return 0;
|
|
}
|
|
|
|
static const struct cgs_ops amdgpu_cgs_ops = {
|
|
.read_register = amdgpu_cgs_read_register,
|
|
.write_register = amdgpu_cgs_write_register,
|
|
.read_ind_register = amdgpu_cgs_read_ind_register,
|
|
.write_ind_register = amdgpu_cgs_write_ind_register,
|
|
.get_firmware_info = amdgpu_cgs_get_firmware_info,
|
|
};
|
|
|
|
struct cgs_device *amdgpu_cgs_create_device(struct amdgpu_device *adev)
|
|
{
|
|
struct amdgpu_cgs_device *cgs_device =
|
|
kmalloc(sizeof(*cgs_device), GFP_KERNEL);
|
|
|
|
if (!cgs_device) {
|
|
DRM_ERROR("Couldn't allocate CGS device structure\n");
|
|
return NULL;
|
|
}
|
|
|
|
cgs_device->base.ops = &amdgpu_cgs_ops;
|
|
cgs_device->adev = adev;
|
|
|
|
return (struct cgs_device *)cgs_device;
|
|
}
|
|
|
|
void amdgpu_cgs_destroy_device(struct cgs_device *cgs_device)
|
|
{
|
|
kfree(cgs_device);
|
|
}
|