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b1b6802586
Between the addition of the ecm/mcm law nodes and the fact that the
get_immrbase() has been using the range property of the SoC to determine
the base address of CCSR space we no longer need the reg property at
the soc node level. It has been ill specified and varied between device
trees to cover either the {e,m}cm-law node, some odd subset of CCSR
space or all of CCSR space.
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
809 lines
18 KiB
Plaintext
809 lines
18 KiB
Plaintext
/*
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* MPC8572 DS Device Tree Source
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*
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* Copyright 2007-2009 Freescale Semiconductor Inc.
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of the GNU General Public License as published by the
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* Free Software Foundation; either version 2 of the License, or (at your
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* option) any later version.
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*/
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/dts-v1/;
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/ {
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model = "fsl,MPC8572DS";
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compatible = "fsl,MPC8572DS";
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#address-cells = <2>;
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#size-cells = <2>;
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aliases {
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ethernet0 = &enet0;
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ethernet1 = &enet1;
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ethernet2 = &enet2;
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ethernet3 = &enet3;
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serial0 = &serial0;
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serial1 = &serial1;
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pci0 = &pci0;
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pci1 = &pci1;
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pci2 = &pci2;
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};
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cpus {
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#address-cells = <1>;
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#size-cells = <0>;
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PowerPC,8572@0 {
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device_type = "cpu";
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reg = <0x0>;
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d-cache-line-size = <32>; // 32 bytes
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i-cache-line-size = <32>; // 32 bytes
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d-cache-size = <0x8000>; // L1, 32K
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i-cache-size = <0x8000>; // L1, 32K
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timebase-frequency = <0>;
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bus-frequency = <0>;
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clock-frequency = <0>;
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next-level-cache = <&L2>;
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};
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PowerPC,8572@1 {
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device_type = "cpu";
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reg = <0x1>;
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d-cache-line-size = <32>; // 32 bytes
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i-cache-line-size = <32>; // 32 bytes
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d-cache-size = <0x8000>; // L1, 32K
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i-cache-size = <0x8000>; // L1, 32K
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timebase-frequency = <0>;
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bus-frequency = <0>;
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clock-frequency = <0>;
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next-level-cache = <&L2>;
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};
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};
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memory {
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device_type = "memory";
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};
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localbus@ffe05000 {
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#address-cells = <2>;
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#size-cells = <1>;
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compatible = "fsl,mpc8572-elbc", "fsl,elbc", "simple-bus";
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reg = <0 0xffe05000 0 0x1000>;
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interrupts = <19 2>;
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interrupt-parent = <&mpic>;
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ranges = <0x0 0x0 0x0 0xe8000000 0x08000000
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0x1 0x0 0x0 0xe0000000 0x08000000
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0x2 0x0 0x0 0xffa00000 0x00040000
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0x3 0x0 0x0 0xffdf0000 0x00008000
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0x4 0x0 0x0 0xffa40000 0x00040000
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0x5 0x0 0x0 0xffa80000 0x00040000
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0x6 0x0 0x0 0xffac0000 0x00040000>;
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nor@0,0 {
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#address-cells = <1>;
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#size-cells = <1>;
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compatible = "cfi-flash";
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reg = <0x0 0x0 0x8000000>;
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bank-width = <2>;
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device-width = <1>;
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ramdisk@0 {
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reg = <0x0 0x03000000>;
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read-only;
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};
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diagnostic@3000000 {
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reg = <0x03000000 0x00e00000>;
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read-only;
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};
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dink@3e00000 {
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reg = <0x03e00000 0x00200000>;
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read-only;
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};
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kernel@4000000 {
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reg = <0x04000000 0x00400000>;
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read-only;
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};
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jffs2@4400000 {
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reg = <0x04400000 0x03b00000>;
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};
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dtb@7f00000 {
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reg = <0x07f00000 0x00080000>;
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read-only;
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};
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u-boot@7f80000 {
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reg = <0x07f80000 0x00080000>;
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read-only;
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};
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};
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nand@2,0 {
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#address-cells = <1>;
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#size-cells = <1>;
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compatible = "fsl,mpc8572-fcm-nand",
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"fsl,elbc-fcm-nand";
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reg = <0x2 0x0 0x40000>;
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u-boot@0 {
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reg = <0x0 0x02000000>;
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read-only;
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};
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jffs2@2000000 {
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reg = <0x02000000 0x10000000>;
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};
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ramdisk@12000000 {
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reg = <0x12000000 0x08000000>;
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read-only;
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};
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kernel@1a000000 {
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reg = <0x1a000000 0x04000000>;
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};
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dtb@1e000000 {
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reg = <0x1e000000 0x01000000>;
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read-only;
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};
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empty@1f000000 {
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reg = <0x1f000000 0x21000000>;
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};
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};
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nand@4,0 {
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compatible = "fsl,mpc8572-fcm-nand",
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"fsl,elbc-fcm-nand";
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reg = <0x4 0x0 0x40000>;
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};
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nand@5,0 {
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compatible = "fsl,mpc8572-fcm-nand",
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"fsl,elbc-fcm-nand";
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reg = <0x5 0x0 0x40000>;
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};
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nand@6,0 {
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compatible = "fsl,mpc8572-fcm-nand",
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"fsl,elbc-fcm-nand";
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reg = <0x6 0x0 0x40000>;
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};
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};
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soc8572@ffe00000 {
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#address-cells = <1>;
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#size-cells = <1>;
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device_type = "soc";
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compatible = "simple-bus";
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ranges = <0x0 0 0xffe00000 0x100000>;
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bus-frequency = <0>; // Filled out by uboot.
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ecm-law@0 {
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compatible = "fsl,ecm-law";
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reg = <0x0 0x1000>;
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fsl,num-laws = <12>;
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};
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ecm@1000 {
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compatible = "fsl,mpc8572-ecm", "fsl,ecm";
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reg = <0x1000 0x1000>;
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interrupts = <17 2>;
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interrupt-parent = <&mpic>;
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};
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memory-controller@2000 {
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compatible = "fsl,mpc8572-memory-controller";
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reg = <0x2000 0x1000>;
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interrupt-parent = <&mpic>;
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interrupts = <18 2>;
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};
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memory-controller@6000 {
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compatible = "fsl,mpc8572-memory-controller";
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reg = <0x6000 0x1000>;
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interrupt-parent = <&mpic>;
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interrupts = <18 2>;
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};
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L2: l2-cache-controller@20000 {
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compatible = "fsl,mpc8572-l2-cache-controller";
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reg = <0x20000 0x1000>;
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cache-line-size = <32>; // 32 bytes
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cache-size = <0x100000>; // L2, 1M
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interrupt-parent = <&mpic>;
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interrupts = <16 2>;
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};
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i2c@3000 {
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#address-cells = <1>;
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#size-cells = <0>;
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cell-index = <0>;
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compatible = "fsl-i2c";
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reg = <0x3000 0x100>;
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interrupts = <43 2>;
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interrupt-parent = <&mpic>;
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dfsrr;
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};
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i2c@3100 {
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#address-cells = <1>;
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#size-cells = <0>;
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cell-index = <1>;
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compatible = "fsl-i2c";
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reg = <0x3100 0x100>;
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interrupts = <43 2>;
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interrupt-parent = <&mpic>;
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dfsrr;
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};
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dma@c300 {
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#address-cells = <1>;
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#size-cells = <1>;
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compatible = "fsl,mpc8572-dma", "fsl,eloplus-dma";
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reg = <0xc300 0x4>;
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ranges = <0x0 0xc100 0x200>;
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cell-index = <1>;
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dma-channel@0 {
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compatible = "fsl,mpc8572-dma-channel",
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"fsl,eloplus-dma-channel";
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reg = <0x0 0x80>;
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cell-index = <0>;
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interrupt-parent = <&mpic>;
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interrupts = <76 2>;
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};
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dma-channel@80 {
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compatible = "fsl,mpc8572-dma-channel",
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"fsl,eloplus-dma-channel";
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reg = <0x80 0x80>;
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cell-index = <1>;
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interrupt-parent = <&mpic>;
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interrupts = <77 2>;
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};
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dma-channel@100 {
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compatible = "fsl,mpc8572-dma-channel",
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"fsl,eloplus-dma-channel";
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reg = <0x100 0x80>;
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cell-index = <2>;
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interrupt-parent = <&mpic>;
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interrupts = <78 2>;
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};
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dma-channel@180 {
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compatible = "fsl,mpc8572-dma-channel",
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"fsl,eloplus-dma-channel";
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reg = <0x180 0x80>;
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cell-index = <3>;
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interrupt-parent = <&mpic>;
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interrupts = <79 2>;
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};
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};
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dma@21300 {
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#address-cells = <1>;
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#size-cells = <1>;
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compatible = "fsl,mpc8572-dma", "fsl,eloplus-dma";
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reg = <0x21300 0x4>;
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ranges = <0x0 0x21100 0x200>;
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cell-index = <0>;
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dma-channel@0 {
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compatible = "fsl,mpc8572-dma-channel",
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"fsl,eloplus-dma-channel";
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reg = <0x0 0x80>;
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cell-index = <0>;
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interrupt-parent = <&mpic>;
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interrupts = <20 2>;
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};
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dma-channel@80 {
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compatible = "fsl,mpc8572-dma-channel",
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"fsl,eloplus-dma-channel";
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reg = <0x80 0x80>;
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cell-index = <1>;
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interrupt-parent = <&mpic>;
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interrupts = <21 2>;
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};
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dma-channel@100 {
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compatible = "fsl,mpc8572-dma-channel",
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"fsl,eloplus-dma-channel";
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reg = <0x100 0x80>;
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cell-index = <2>;
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interrupt-parent = <&mpic>;
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interrupts = <22 2>;
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};
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dma-channel@180 {
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compatible = "fsl,mpc8572-dma-channel",
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"fsl,eloplus-dma-channel";
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reg = <0x180 0x80>;
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cell-index = <3>;
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interrupt-parent = <&mpic>;
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interrupts = <23 2>;
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};
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};
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enet0: ethernet@24000 {
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#address-cells = <1>;
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#size-cells = <1>;
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cell-index = <0>;
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device_type = "network";
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model = "eTSEC";
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compatible = "gianfar";
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reg = <0x24000 0x1000>;
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ranges = <0x0 0x24000 0x1000>;
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local-mac-address = [ 00 00 00 00 00 00 ];
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interrupts = <29 2 30 2 34 2>;
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interrupt-parent = <&mpic>;
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tbi-handle = <&tbi0>;
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phy-handle = <&phy0>;
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phy-connection-type = "rgmii-id";
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mdio@520 {
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#address-cells = <1>;
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#size-cells = <0>;
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compatible = "fsl,gianfar-mdio";
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reg = <0x520 0x20>;
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phy0: ethernet-phy@0 {
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interrupt-parent = <&mpic>;
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interrupts = <10 1>;
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reg = <0x0>;
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};
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phy1: ethernet-phy@1 {
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interrupt-parent = <&mpic>;
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interrupts = <10 1>;
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reg = <0x1>;
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};
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phy2: ethernet-phy@2 {
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interrupt-parent = <&mpic>;
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interrupts = <10 1>;
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reg = <0x2>;
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};
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phy3: ethernet-phy@3 {
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interrupt-parent = <&mpic>;
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interrupts = <10 1>;
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reg = <0x3>;
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};
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tbi0: tbi-phy@11 {
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reg = <0x11>;
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device_type = "tbi-phy";
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};
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};
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};
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enet1: ethernet@25000 {
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#address-cells = <1>;
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#size-cells = <1>;
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cell-index = <1>;
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device_type = "network";
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model = "eTSEC";
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compatible = "gianfar";
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reg = <0x25000 0x1000>;
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ranges = <0x0 0x25000 0x1000>;
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local-mac-address = [ 00 00 00 00 00 00 ];
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interrupts = <35 2 36 2 40 2>;
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interrupt-parent = <&mpic>;
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tbi-handle = <&tbi1>;
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phy-handle = <&phy1>;
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phy-connection-type = "rgmii-id";
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mdio@520 {
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#address-cells = <1>;
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#size-cells = <0>;
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compatible = "fsl,gianfar-tbi";
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reg = <0x520 0x20>;
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tbi1: tbi-phy@11 {
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reg = <0x11>;
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device_type = "tbi-phy";
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};
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};
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};
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enet2: ethernet@26000 {
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#address-cells = <1>;
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#size-cells = <1>;
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cell-index = <2>;
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device_type = "network";
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model = "eTSEC";
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compatible = "gianfar";
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reg = <0x26000 0x1000>;
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ranges = <0x0 0x26000 0x1000>;
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local-mac-address = [ 00 00 00 00 00 00 ];
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interrupts = <31 2 32 2 33 2>;
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interrupt-parent = <&mpic>;
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tbi-handle = <&tbi2>;
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phy-handle = <&phy2>;
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phy-connection-type = "rgmii-id";
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mdio@520 {
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#address-cells = <1>;
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#size-cells = <0>;
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compatible = "fsl,gianfar-tbi";
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reg = <0x520 0x20>;
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tbi2: tbi-phy@11 {
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reg = <0x11>;
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device_type = "tbi-phy";
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};
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};
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};
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enet3: ethernet@27000 {
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#address-cells = <1>;
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#size-cells = <1>;
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cell-index = <3>;
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device_type = "network";
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model = "eTSEC";
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compatible = "gianfar";
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reg = <0x27000 0x1000>;
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ranges = <0x0 0x27000 0x1000>;
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local-mac-address = [ 00 00 00 00 00 00 ];
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interrupts = <37 2 38 2 39 2>;
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interrupt-parent = <&mpic>;
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tbi-handle = <&tbi3>;
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phy-handle = <&phy3>;
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phy-connection-type = "rgmii-id";
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mdio@520 {
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#address-cells = <1>;
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#size-cells = <0>;
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compatible = "fsl,gianfar-tbi";
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reg = <0x520 0x20>;
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tbi3: tbi-phy@11 {
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reg = <0x11>;
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device_type = "tbi-phy";
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};
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};
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};
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serial0: serial@4500 {
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cell-index = <0>;
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device_type = "serial";
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compatible = "ns16550";
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reg = <0x4500 0x100>;
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clock-frequency = <0>;
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interrupts = <42 2>;
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interrupt-parent = <&mpic>;
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};
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serial1: serial@4600 {
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cell-index = <1>;
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device_type = "serial";
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compatible = "ns16550";
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reg = <0x4600 0x100>;
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clock-frequency = <0>;
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interrupts = <42 2>;
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interrupt-parent = <&mpic>;
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};
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global-utilities@e0000 { //global utilities block
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compatible = "fsl,mpc8572-guts";
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reg = <0xe0000 0x1000>;
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fsl,has-rstcr;
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};
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msi@41600 {
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compatible = "fsl,mpc8572-msi", "fsl,mpic-msi";
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reg = <0x41600 0x80>;
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msi-available-ranges = <0 0x100>;
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interrupts = <
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0xe0 0
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0xe1 0
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0xe2 0
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0xe3 0
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0xe4 0
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0xe5 0
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0xe6 0
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0xe7 0>;
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interrupt-parent = <&mpic>;
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};
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crypto@30000 {
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compatible = "fsl,sec3.0", "fsl,sec2.4", "fsl,sec2.2",
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"fsl,sec2.1", "fsl,sec2.0";
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reg = <0x30000 0x10000>;
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interrupts = <45 2 58 2>;
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interrupt-parent = <&mpic>;
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fsl,num-channels = <4>;
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fsl,channel-fifo-len = <24>;
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fsl,exec-units-mask = <0x9fe>;
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fsl,descriptor-types-mask = <0x3ab0ebf>;
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};
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mpic: pic@40000 {
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interrupt-controller;
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#address-cells = <0>;
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#interrupt-cells = <2>;
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reg = <0x40000 0x40000>;
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compatible = "chrp,open-pic";
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device_type = "open-pic";
|
|
};
|
|
};
|
|
|
|
pci0: pcie@ffe08000 {
|
|
compatible = "fsl,mpc8548-pcie";
|
|
device_type = "pci";
|
|
#interrupt-cells = <1>;
|
|
#size-cells = <2>;
|
|
#address-cells = <3>;
|
|
reg = <0 0xffe08000 0 0x1000>;
|
|
bus-range = <0 255>;
|
|
ranges = <0x2000000 0x0 0x80000000 0 0x80000000 0x0 0x20000000
|
|
0x1000000 0x0 0x00000000 0 0xffc00000 0x0 0x00010000>;
|
|
clock-frequency = <33333333>;
|
|
interrupt-parent = <&mpic>;
|
|
interrupts = <24 2>;
|
|
interrupt-map-mask = <0xff00 0x0 0x0 0x7>;
|
|
interrupt-map = <
|
|
/* IDSEL 0x11 func 0 - PCI slot 1 */
|
|
0x8800 0x0 0x0 0x1 &mpic 0x2 0x1
|
|
0x8800 0x0 0x0 0x2 &mpic 0x3 0x1
|
|
0x8800 0x0 0x0 0x3 &mpic 0x4 0x1
|
|
0x8800 0x0 0x0 0x4 &mpic 0x1 0x1
|
|
|
|
/* IDSEL 0x11 func 1 - PCI slot 1 */
|
|
0x8900 0x0 0x0 0x1 &mpic 0x2 0x1
|
|
0x8900 0x0 0x0 0x2 &mpic 0x3 0x1
|
|
0x8900 0x0 0x0 0x3 &mpic 0x4 0x1
|
|
0x8900 0x0 0x0 0x4 &mpic 0x1 0x1
|
|
|
|
/* IDSEL 0x11 func 2 - PCI slot 1 */
|
|
0x8a00 0x0 0x0 0x1 &mpic 0x2 0x1
|
|
0x8a00 0x0 0x0 0x2 &mpic 0x3 0x1
|
|
0x8a00 0x0 0x0 0x3 &mpic 0x4 0x1
|
|
0x8a00 0x0 0x0 0x4 &mpic 0x1 0x1
|
|
|
|
/* IDSEL 0x11 func 3 - PCI slot 1 */
|
|
0x8b00 0x0 0x0 0x1 &mpic 0x2 0x1
|
|
0x8b00 0x0 0x0 0x2 &mpic 0x3 0x1
|
|
0x8b00 0x0 0x0 0x3 &mpic 0x4 0x1
|
|
0x8b00 0x0 0x0 0x4 &mpic 0x1 0x1
|
|
|
|
/* IDSEL 0x11 func 4 - PCI slot 1 */
|
|
0x8c00 0x0 0x0 0x1 &mpic 0x2 0x1
|
|
0x8c00 0x0 0x0 0x2 &mpic 0x3 0x1
|
|
0x8c00 0x0 0x0 0x3 &mpic 0x4 0x1
|
|
0x8c00 0x0 0x0 0x4 &mpic 0x1 0x1
|
|
|
|
/* IDSEL 0x11 func 5 - PCI slot 1 */
|
|
0x8d00 0x0 0x0 0x1 &mpic 0x2 0x1
|
|
0x8d00 0x0 0x0 0x2 &mpic 0x3 0x1
|
|
0x8d00 0x0 0x0 0x3 &mpic 0x4 0x1
|
|
0x8d00 0x0 0x0 0x4 &mpic 0x1 0x1
|
|
|
|
/* IDSEL 0x11 func 6 - PCI slot 1 */
|
|
0x8e00 0x0 0x0 0x1 &mpic 0x2 0x1
|
|
0x8e00 0x0 0x0 0x2 &mpic 0x3 0x1
|
|
0x8e00 0x0 0x0 0x3 &mpic 0x4 0x1
|
|
0x8e00 0x0 0x0 0x4 &mpic 0x1 0x1
|
|
|
|
/* IDSEL 0x11 func 7 - PCI slot 1 */
|
|
0x8f00 0x0 0x0 0x1 &mpic 0x2 0x1
|
|
0x8f00 0x0 0x0 0x2 &mpic 0x3 0x1
|
|
0x8f00 0x0 0x0 0x3 &mpic 0x4 0x1
|
|
0x8f00 0x0 0x0 0x4 &mpic 0x1 0x1
|
|
|
|
/* IDSEL 0x12 func 0 - PCI slot 2 */
|
|
0x9000 0x0 0x0 0x1 &mpic 0x3 0x1
|
|
0x9000 0x0 0x0 0x2 &mpic 0x4 0x1
|
|
0x9000 0x0 0x0 0x3 &mpic 0x1 0x1
|
|
0x9000 0x0 0x0 0x4 &mpic 0x2 0x1
|
|
|
|
/* IDSEL 0x12 func 1 - PCI slot 2 */
|
|
0x9100 0x0 0x0 0x1 &mpic 0x3 0x1
|
|
0x9100 0x0 0x0 0x2 &mpic 0x4 0x1
|
|
0x9100 0x0 0x0 0x3 &mpic 0x1 0x1
|
|
0x9100 0x0 0x0 0x4 &mpic 0x2 0x1
|
|
|
|
/* IDSEL 0x12 func 2 - PCI slot 2 */
|
|
0x9200 0x0 0x0 0x1 &mpic 0x3 0x1
|
|
0x9200 0x0 0x0 0x2 &mpic 0x4 0x1
|
|
0x9200 0x0 0x0 0x3 &mpic 0x1 0x1
|
|
0x9200 0x0 0x0 0x4 &mpic 0x2 0x1
|
|
|
|
/* IDSEL 0x12 func 3 - PCI slot 2 */
|
|
0x9300 0x0 0x0 0x1 &mpic 0x3 0x1
|
|
0x9300 0x0 0x0 0x2 &mpic 0x4 0x1
|
|
0x9300 0x0 0x0 0x3 &mpic 0x1 0x1
|
|
0x9300 0x0 0x0 0x4 &mpic 0x2 0x1
|
|
|
|
/* IDSEL 0x12 func 4 - PCI slot 2 */
|
|
0x9400 0x0 0x0 0x1 &mpic 0x3 0x1
|
|
0x9400 0x0 0x0 0x2 &mpic 0x4 0x1
|
|
0x9400 0x0 0x0 0x3 &mpic 0x1 0x1
|
|
0x9400 0x0 0x0 0x4 &mpic 0x2 0x1
|
|
|
|
/* IDSEL 0x12 func 5 - PCI slot 2 */
|
|
0x9500 0x0 0x0 0x1 &mpic 0x3 0x1
|
|
0x9500 0x0 0x0 0x2 &mpic 0x4 0x1
|
|
0x9500 0x0 0x0 0x3 &mpic 0x1 0x1
|
|
0x9500 0x0 0x0 0x4 &mpic 0x2 0x1
|
|
|
|
/* IDSEL 0x12 func 6 - PCI slot 2 */
|
|
0x9600 0x0 0x0 0x1 &mpic 0x3 0x1
|
|
0x9600 0x0 0x0 0x2 &mpic 0x4 0x1
|
|
0x9600 0x0 0x0 0x3 &mpic 0x1 0x1
|
|
0x9600 0x0 0x0 0x4 &mpic 0x2 0x1
|
|
|
|
/* IDSEL 0x12 func 7 - PCI slot 2 */
|
|
0x9700 0x0 0x0 0x1 &mpic 0x3 0x1
|
|
0x9700 0x0 0x0 0x2 &mpic 0x4 0x1
|
|
0x9700 0x0 0x0 0x3 &mpic 0x1 0x1
|
|
0x9700 0x0 0x0 0x4 &mpic 0x2 0x1
|
|
|
|
// IDSEL 0x1c USB
|
|
0xe000 0x0 0x0 0x1 &i8259 0xc 0x2
|
|
0xe100 0x0 0x0 0x2 &i8259 0x9 0x2
|
|
0xe200 0x0 0x0 0x3 &i8259 0xa 0x2
|
|
0xe300 0x0 0x0 0x4 &i8259 0xb 0x2
|
|
|
|
// IDSEL 0x1d Audio
|
|
0xe800 0x0 0x0 0x1 &i8259 0x6 0x2
|
|
|
|
// IDSEL 0x1e Legacy
|
|
0xf000 0x0 0x0 0x1 &i8259 0x7 0x2
|
|
0xf100 0x0 0x0 0x1 &i8259 0x7 0x2
|
|
|
|
// IDSEL 0x1f IDE/SATA
|
|
0xf800 0x0 0x0 0x1 &i8259 0xe 0x2
|
|
0xf900 0x0 0x0 0x1 &i8259 0x5 0x2
|
|
|
|
>;
|
|
|
|
pcie@0 {
|
|
reg = <0x0 0x0 0x0 0x0 0x0>;
|
|
#size-cells = <2>;
|
|
#address-cells = <3>;
|
|
device_type = "pci";
|
|
ranges = <0x2000000 0x0 0x80000000
|
|
0x2000000 0x0 0x80000000
|
|
0x0 0x20000000
|
|
|
|
0x1000000 0x0 0x0
|
|
0x1000000 0x0 0x0
|
|
0x0 0x10000>;
|
|
uli1575@0 {
|
|
reg = <0x0 0x0 0x0 0x0 0x0>;
|
|
#size-cells = <2>;
|
|
#address-cells = <3>;
|
|
ranges = <0x2000000 0x0 0x80000000
|
|
0x2000000 0x0 0x80000000
|
|
0x0 0x20000000
|
|
|
|
0x1000000 0x0 0x0
|
|
0x1000000 0x0 0x0
|
|
0x0 0x10000>;
|
|
isa@1e {
|
|
device_type = "isa";
|
|
#interrupt-cells = <2>;
|
|
#size-cells = <1>;
|
|
#address-cells = <2>;
|
|
reg = <0xf000 0x0 0x0 0x0 0x0>;
|
|
ranges = <0x1 0x0 0x1000000 0x0 0x0
|
|
0x1000>;
|
|
interrupt-parent = <&i8259>;
|
|
|
|
i8259: interrupt-controller@20 {
|
|
reg = <0x1 0x20 0x2
|
|
0x1 0xa0 0x2
|
|
0x1 0x4d0 0x2>;
|
|
interrupt-controller;
|
|
device_type = "interrupt-controller";
|
|
#address-cells = <0>;
|
|
#interrupt-cells = <2>;
|
|
compatible = "chrp,iic";
|
|
interrupts = <9 2>;
|
|
interrupt-parent = <&mpic>;
|
|
};
|
|
|
|
i8042@60 {
|
|
#size-cells = <0>;
|
|
#address-cells = <1>;
|
|
reg = <0x1 0x60 0x1 0x1 0x64 0x1>;
|
|
interrupts = <1 3 12 3>;
|
|
interrupt-parent =
|
|
<&i8259>;
|
|
|
|
keyboard@0 {
|
|
reg = <0x0>;
|
|
compatible = "pnpPNP,303";
|
|
};
|
|
|
|
mouse@1 {
|
|
reg = <0x1>;
|
|
compatible = "pnpPNP,f03";
|
|
};
|
|
};
|
|
|
|
rtc@70 {
|
|
compatible = "pnpPNP,b00";
|
|
reg = <0x1 0x70 0x2>;
|
|
};
|
|
|
|
gpio@400 {
|
|
reg = <0x1 0x400 0x80>;
|
|
};
|
|
};
|
|
};
|
|
};
|
|
|
|
};
|
|
|
|
pci1: pcie@ffe09000 {
|
|
compatible = "fsl,mpc8548-pcie";
|
|
device_type = "pci";
|
|
#interrupt-cells = <1>;
|
|
#size-cells = <2>;
|
|
#address-cells = <3>;
|
|
reg = <0 0xffe09000 0 0x1000>;
|
|
bus-range = <0 255>;
|
|
ranges = <0x2000000 0x0 0xa0000000 0 0xa0000000 0x0 0x20000000
|
|
0x1000000 0x0 0x00000000 0 0xffc10000 0x0 0x00010000>;
|
|
clock-frequency = <33333333>;
|
|
interrupt-parent = <&mpic>;
|
|
interrupts = <25 2>;
|
|
interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
|
|
interrupt-map = <
|
|
/* IDSEL 0x0 */
|
|
0000 0x0 0x0 0x1 &mpic 0x4 0x1
|
|
0000 0x0 0x0 0x2 &mpic 0x5 0x1
|
|
0000 0x0 0x0 0x3 &mpic 0x6 0x1
|
|
0000 0x0 0x0 0x4 &mpic 0x7 0x1
|
|
>;
|
|
pcie@0 {
|
|
reg = <0x0 0x0 0x0 0x0 0x0>;
|
|
#size-cells = <2>;
|
|
#address-cells = <3>;
|
|
device_type = "pci";
|
|
ranges = <0x2000000 0x0 0xa0000000
|
|
0x2000000 0x0 0xa0000000
|
|
0x0 0x20000000
|
|
|
|
0x1000000 0x0 0x0
|
|
0x1000000 0x0 0x0
|
|
0x0 0x10000>;
|
|
};
|
|
};
|
|
|
|
pci2: pcie@ffe0a000 {
|
|
compatible = "fsl,mpc8548-pcie";
|
|
device_type = "pci";
|
|
#interrupt-cells = <1>;
|
|
#size-cells = <2>;
|
|
#address-cells = <3>;
|
|
reg = <0 0xffe0a000 0 0x1000>;
|
|
bus-range = <0 255>;
|
|
ranges = <0x2000000 0x0 0xc0000000 0 0xc0000000 0x0 0x20000000
|
|
0x1000000 0x0 0x00000000 0 0xffc20000 0x0 0x00010000>;
|
|
clock-frequency = <33333333>;
|
|
interrupt-parent = <&mpic>;
|
|
interrupts = <26 2>;
|
|
interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
|
|
interrupt-map = <
|
|
/* IDSEL 0x0 */
|
|
0000 0x0 0x0 0x1 &mpic 0x0 0x1
|
|
0000 0x0 0x0 0x2 &mpic 0x1 0x1
|
|
0000 0x0 0x0 0x3 &mpic 0x2 0x1
|
|
0000 0x0 0x0 0x4 &mpic 0x3 0x1
|
|
>;
|
|
pcie@0 {
|
|
reg = <0x0 0x0 0x0 0x0 0x0>;
|
|
#size-cells = <2>;
|
|
#address-cells = <3>;
|
|
device_type = "pci";
|
|
ranges = <0x2000000 0x0 0xc0000000
|
|
0x2000000 0x0 0xc0000000
|
|
0x0 0x20000000
|
|
|
|
0x1000000 0x0 0x0
|
|
0x1000000 0x0 0x0
|
|
0x0 0x10000>;
|
|
};
|
|
};
|
|
};
|