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6dacafea2d
Various registers to control and check AIC status. Signed-off-by: Sujith Manoharan <c_manoha@qca.qualcomm.com> Signed-off-by: Kalle Valo <kvalo@codeaurora.org>
169 lines
8.5 KiB
C
169 lines
8.5 KiB
C
/*
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* Copyright (c) 2015 Qualcomm Atheros Inc.
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*
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* Permission to use, copy, modify, and/or distribute this software for any
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* purpose with or without fee is hereby granted, provided that the above
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* copyright notice and this permission notice appear in all copies.
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*
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* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
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* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
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* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
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* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
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* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
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* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
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* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
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*/
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#ifndef REG_AIC_H
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#define REG_AIC_H
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#define AR_SM_BASE 0xa200
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#define AR_SM1_BASE 0xb200
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#define AR_AGC_BASE 0x9e00
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#define AR_PHY_AIC_CTRL_0_B0 (AR_SM_BASE + 0x4b0)
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#define AR_PHY_AIC_CTRL_1_B0 (AR_SM_BASE + 0x4b4)
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#define AR_PHY_AIC_CTRL_2_B0 (AR_SM_BASE + 0x4b8)
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#define AR_PHY_AIC_CTRL_3_B0 (AR_SM_BASE + 0x4bc)
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#define AR_PHY_AIC_CTRL_4_B0 (AR_SM_BASE + 0x4c0)
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#define AR_PHY_AIC_STAT_0_B0 (AR_SM_BASE + 0x4c4)
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#define AR_PHY_AIC_STAT_1_B0 (AR_SM_BASE + 0x4c8)
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#define AR_PHY_AIC_STAT_2_B0 (AR_SM_BASE + 0x4cc)
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#define AR_PHY_AIC_CTRL_0_B1 (AR_SM1_BASE + 0x4b0)
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#define AR_PHY_AIC_CTRL_1_B1 (AR_SM1_BASE + 0x4b4)
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#define AR_PHY_AIC_CTRL_4_B1 (AR_SM1_BASE + 0x4c0)
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#define AR_PHY_AIC_STAT_0_B1 (AR_SM1_BASE + 0x4c4)
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#define AR_PHY_AIC_STAT_1_B1 (AR_SM1_BASE + 0x4c8)
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#define AR_PHY_AIC_STAT_2_B1 (AR_SM1_BASE + 0x4cc)
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#define AR_PHY_AIC_SRAM_ADDR_B0 (AR_SM_BASE + 0x5f0)
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#define AR_PHY_AIC_SRAM_DATA_B0 (AR_SM_BASE + 0x5f4)
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#define AR_PHY_AIC_SRAM_ADDR_B1 (AR_SM1_BASE + 0x5f0)
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#define AR_PHY_AIC_SRAM_DATA_B1 (AR_SM1_BASE + 0x5f4)
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#define AR_PHY_BT_COEX_4 (AR_AGC_BASE + 0x60)
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#define AR_PHY_BT_COEX_5 (AR_AGC_BASE + 0x64)
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/* AIC fields */
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#define AR_PHY_AIC_MON_ENABLE 0x80000000
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#define AR_PHY_AIC_MON_ENABLE_S 31
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#define AR_PHY_AIC_CAL_MAX_HOP_COUNT 0x7F000000
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#define AR_PHY_AIC_CAL_MAX_HOP_COUNT_S 24
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#define AR_PHY_AIC_CAL_MIN_VALID_COUNT 0x00FE0000
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#define AR_PHY_AIC_CAL_MIN_VALID_COUNT_S 17
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#define AR_PHY_AIC_F_WLAN 0x0001FC00
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#define AR_PHY_AIC_F_WLAN_S 10
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#define AR_PHY_AIC_CAL_CH_VALID_RESET 0x00000200
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#define AR_PHY_AIC_CAL_CH_VALID_RESET_S 9
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#define AR_PHY_AIC_CAL_ENABLE 0x00000100
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#define AR_PHY_AIC_CAL_ENABLE_S 8
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#define AR_PHY_AIC_BTTX_PWR_THR 0x000000FE
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#define AR_PHY_AIC_BTTX_PWR_THR_S 1
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#define AR_PHY_AIC_ENABLE 0x00000001
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#define AR_PHY_AIC_ENABLE_S 0
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#define AR_PHY_AIC_CAL_BT_REF_DELAY 0x00F00000
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#define AR_PHY_AIC_CAL_BT_REF_DELAY_S 20
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#define AR_PHY_AIC_BT_IDLE_CFG 0x00080000
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#define AR_PHY_AIC_BT_IDLE_CFG_S 19
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#define AR_PHY_AIC_STDBY_COND 0x00060000
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#define AR_PHY_AIC_STDBY_COND_S 17
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#define AR_PHY_AIC_STDBY_ROT_ATT_DB 0x0001F800
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#define AR_PHY_AIC_STDBY_ROT_ATT_DB_S 11
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#define AR_PHY_AIC_STDBY_COM_ATT_DB 0x00000700
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#define AR_PHY_AIC_STDBY_COM_ATT_DB_S 8
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#define AR_PHY_AIC_RSSI_MAX 0x000000F0
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#define AR_PHY_AIC_RSSI_MAX_S 4
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#define AR_PHY_AIC_RSSI_MIN 0x0000000F
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#define AR_PHY_AIC_RSSI_MIN_S 0
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#define AR_PHY_AIC_RADIO_DELAY 0x7F000000
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#define AR_PHY_AIC_RADIO_DELAY_S 24
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#define AR_PHY_AIC_CAL_STEP_SIZE_CORR 0x00F00000
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#define AR_PHY_AIC_CAL_STEP_SIZE_CORR_S 20
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#define AR_PHY_AIC_CAL_ROT_IDX_CORR 0x000F8000
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#define AR_PHY_AIC_CAL_ROT_IDX_CORR_S 15
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#define AR_PHY_AIC_CAL_CONV_CHECK_FACTOR 0x00006000
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#define AR_PHY_AIC_CAL_CONV_CHECK_FACTOR_S 13
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#define AR_PHY_AIC_ROT_IDX_COUNT_MAX 0x00001C00
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#define AR_PHY_AIC_ROT_IDX_COUNT_MAX_S 10
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#define AR_PHY_AIC_CAL_SYNTH_TOGGLE 0x00000200
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#define AR_PHY_AIC_CAL_SYNTH_TOGGLE_S 9
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#define AR_PHY_AIC_CAL_SYNTH_AFTER_BTRX 0x00000100
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#define AR_PHY_AIC_CAL_SYNTH_AFTER_BTRX_S 8
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#define AR_PHY_AIC_CAL_SYNTH_SETTLING 0x000000FF
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#define AR_PHY_AIC_CAL_SYNTH_SETTLING_S 0
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#define AR_PHY_AIC_MON_MAX_HOP_COUNT 0x07F00000
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#define AR_PHY_AIC_MON_MAX_HOP_COUNT_S 20
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#define AR_PHY_AIC_MON_MIN_STALE_COUNT 0x000FE000
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#define AR_PHY_AIC_MON_MIN_STALE_COUNT_S 13
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#define AR_PHY_AIC_MON_PWR_EST_LONG 0x00001000
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#define AR_PHY_AIC_MON_PWR_EST_LONG_S 12
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#define AR_PHY_AIC_MON_PD_TALLY_SCALING 0x00000C00
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#define AR_PHY_AIC_MON_PD_TALLY_SCALING_S 10
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#define AR_PHY_AIC_MON_PERF_THR 0x000003E0
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#define AR_PHY_AIC_MON_PERF_THR_S 5
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#define AR_PHY_AIC_CAL_TARGET_MAG_SETTING 0x00000018
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#define AR_PHY_AIC_CAL_TARGET_MAG_SETTING_S 3
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#define AR_PHY_AIC_CAL_PERF_CHECK_FACTOR 0x00000006
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#define AR_PHY_AIC_CAL_PERF_CHECK_FACTOR_S 1
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#define AR_PHY_AIC_CAL_PWR_EST_LONG 0x00000001
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#define AR_PHY_AIC_CAL_PWR_EST_LONG_S 0
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#define AR_PHY_AIC_MON_DONE 0x80000000
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#define AR_PHY_AIC_MON_DONE_S 31
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#define AR_PHY_AIC_MON_ACTIVE 0x40000000
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#define AR_PHY_AIC_MON_ACTIVE_S 30
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#define AR_PHY_AIC_MEAS_COUNT 0x3F000000
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#define AR_PHY_AIC_MEAS_COUNT_S 24
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#define AR_PHY_AIC_CAL_ANT_ISO_EST 0x00FC0000
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#define AR_PHY_AIC_CAL_ANT_ISO_EST_S 18
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#define AR_PHY_AIC_CAL_HOP_COUNT 0x0003F800
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#define AR_PHY_AIC_CAL_HOP_COUNT_S 11
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#define AR_PHY_AIC_CAL_VALID_COUNT 0x000007F0
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#define AR_PHY_AIC_CAL_VALID_COUNT_S 4
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#define AR_PHY_AIC_CAL_BT_TOO_WEAK_ERR 0x00000008
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#define AR_PHY_AIC_CAL_BT_TOO_WEAK_ERR_S 3
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#define AR_PHY_AIC_CAL_BT_TOO_STRONG_ERR 0x00000004
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#define AR_PHY_AIC_CAL_BT_TOO_STRONG_ERR_S 2
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#define AR_PHY_AIC_CAL_DONE 0x00000002
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#define AR_PHY_AIC_CAL_DONE_S 1
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#define AR_PHY_AIC_CAL_ACTIVE 0x00000001
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#define AR_PHY_AIC_CAL_ACTIVE_S 0
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#define AR_PHY_AIC_MEAS_MAG_MIN 0xFFC00000
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#define AR_PHY_AIC_MEAS_MAG_MIN_S 22
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#define AR_PHY_AIC_MON_STALE_COUNT 0x003F8000
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#define AR_PHY_AIC_MON_STALE_COUNT_S 15
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#define AR_PHY_AIC_MON_HOP_COUNT 0x00007F00
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#define AR_PHY_AIC_MON_HOP_COUNT_S 8
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#define AR_PHY_AIC_CAL_AIC_SM 0x000000F8
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#define AR_PHY_AIC_CAL_AIC_SM_S 3
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#define AR_PHY_AIC_SM 0x00000007
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#define AR_PHY_AIC_SM_S 0
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#define AR_PHY_AIC_SRAM_VALID 0x00000001
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#define AR_PHY_AIC_SRAM_VALID_S 0
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#define AR_PHY_AIC_SRAM_ROT_QUAD_ATT_DB 0x0000007E
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#define AR_PHY_AIC_SRAM_ROT_QUAD_ATT_DB_S 1
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#define AR_PHY_AIC_SRAM_VGA_QUAD_SIGN 0x00000080
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#define AR_PHY_AIC_SRAM_VGA_QUAD_SIGN_S 7
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#define AR_PHY_AIC_SRAM_ROT_DIR_ATT_DB 0x00003F00
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#define AR_PHY_AIC_SRAM_ROT_DIR_ATT_DB_S 8
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#define AR_PHY_AIC_SRAM_VGA_DIR_SIGN 0x00004000
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#define AR_PHY_AIC_SRAM_VGA_DIR_SIGN_S 14
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#define AR_PHY_AIC_SRAM_COM_ATT_6DB 0x00038000
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#define AR_PHY_AIC_SRAM_COM_ATT_6DB_S 15
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#define AR_PHY_AIC_CAL_ROT_ATT_DB_EST_ISO 0x0000E000
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#define AR_PHY_AIC_CAL_ROT_ATT_DB_EST_ISO_S 13
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#define AR_PHY_AIC_CAL_COM_ATT_DB_EST_ISO 0x00001E00
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#define AR_PHY_AIC_CAL_COM_ATT_DB_EST_ISO_S 9
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#define AR_PHY_AIC_CAL_ISO_EST_INIT_SETTING 0x000001F8
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#define AR_PHY_AIC_CAL_ISO_EST_INIT_SETTING_S 3
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#define AR_PHY_AIC_CAL_COM_ATT_DB_BACKOFF 0x00000006
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#define AR_PHY_AIC_CAL_COM_ATT_DB_BACKOFF_S 1
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#define AR_PHY_AIC_CAL_COM_ATT_DB_FIXED 0x00000001
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#define AR_PHY_AIC_CAL_COM_ATT_DB_FIXED_S 0
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#endif /* REG_AIC_H */
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