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5c6201e60a
I made a mistake as for naming for this block. The MIO block is not implemented for these 3 SoCs in the first place. The current naming will be a trouble if an SoC with both MIO and SD-ctrl blocks appear in the future. This driver has just been merged in the previous merge window. Rename it before the release. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
135 lines
3.0 KiB
Plaintext
135 lines
3.0 KiB
Plaintext
UniPhier clock controller
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System clock
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------------
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Required properties:
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- compatible: should be one of the following:
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"socionext,uniphier-sld3-clock" - for sLD3 SoC.
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"socionext,uniphier-ld4-clock" - for LD4 SoC.
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"socionext,uniphier-pro4-clock" - for Pro4 SoC.
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"socionext,uniphier-sld8-clock" - for sLD8 SoC.
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"socionext,uniphier-pro5-clock" - for Pro5 SoC.
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"socionext,uniphier-pxs2-clock" - for PXs2/LD6b SoC.
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"socionext,uniphier-ld11-clock" - for LD11 SoC.
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"socionext,uniphier-ld20-clock" - for LD20 SoC.
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- #clock-cells: should be 1.
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Example:
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sysctrl@61840000 {
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compatible = "socionext,uniphier-sysctrl",
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"simple-mfd", "syscon";
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reg = <0x61840000 0x4000>;
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clock {
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compatible = "socionext,uniphier-ld11-clock";
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#clock-cells = <1>;
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};
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other nodes ...
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};
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Provided clocks:
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8: ST DMAC
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12: GIO (Giga bit stream I/O)
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14: USB3 ch0 host
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15: USB3 ch1 host
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16: USB3 ch0 PHY0
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17: USB3 ch0 PHY1
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20: USB3 ch1 PHY0
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21: USB3 ch1 PHY1
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Media I/O (MIO) clock, SD clock
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-------------------------------
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Required properties:
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- compatible: should be one of the following:
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"socionext,uniphier-sld3-mio-clock" - for sLD3 SoC.
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"socionext,uniphier-ld4-mio-clock" - for LD4 SoC.
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"socionext,uniphier-pro4-mio-clock" - for Pro4 SoC.
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"socionext,uniphier-sld8-mio-clock" - for sLD8 SoC.
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"socionext,uniphier-pro5-sd-clock" - for Pro5 SoC.
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"socionext,uniphier-pxs2-sd-clock" - for PXs2/LD6b SoC.
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"socionext,uniphier-ld11-mio-clock" - for LD11 SoC.
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"socionext,uniphier-ld20-sd-clock" - for LD20 SoC.
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- #clock-cells: should be 1.
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Example:
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mioctrl@59810000 {
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compatible = "socionext,uniphier-mioctrl",
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"simple-mfd", "syscon";
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reg = <0x59810000 0x800>;
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clock {
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compatible = "socionext,uniphier-ld11-mio-clock";
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#clock-cells = <1>;
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};
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other nodes ...
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};
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Provided clocks:
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0: SD ch0 host
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1: eMMC host
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2: SD ch1 host
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7: MIO DMAC
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8: USB2 ch0 host
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9: USB2 ch1 host
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10: USB2 ch2 host
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11: USB2 ch3 host
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12: USB2 ch0 PHY
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13: USB2 ch1 PHY
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14: USB2 ch2 PHY
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15: USB2 ch3 PHY
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Peripheral clock
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----------------
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Required properties:
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- compatible: should be one of the following:
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"socionext,uniphier-sld3-peri-clock" - for sLD3 SoC.
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"socionext,uniphier-ld4-peri-clock" - for LD4 SoC.
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"socionext,uniphier-pro4-peri-clock" - for Pro4 SoC.
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"socionext,uniphier-sld8-peri-clock" - for sLD8 SoC.
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"socionext,uniphier-pro5-peri-clock" - for Pro5 SoC.
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"socionext,uniphier-pxs2-peri-clock" - for PXs2/LD6b SoC.
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"socionext,uniphier-ld11-peri-clock" - for LD11 SoC.
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"socionext,uniphier-ld20-peri-clock" - for LD20 SoC.
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- #clock-cells: should be 1.
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Example:
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perictrl@59820000 {
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compatible = "socionext,uniphier-perictrl",
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"simple-mfd", "syscon";
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reg = <0x59820000 0x200>;
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clock {
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compatible = "socionext,uniphier-ld11-peri-clock";
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#clock-cells = <1>;
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};
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other nodes ...
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};
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Provided clocks:
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0: UART ch0
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1: UART ch1
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2: UART ch2
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3: UART ch3
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4: I2C ch0
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5: I2C ch1
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6: I2C ch2
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7: I2C ch3
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8: I2C ch4
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9: I2C ch5
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10: I2C ch6
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