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260cf8a2cb
Comparing the layouts of struct detail_pixel_timing with x.org's struct detailed_timings and how those are handled, it appears that the hsync_positive and vsync_positive fields are backwards. This patch fixes https://bugs.freedesktop.org/show_bug.cgi?id=20019 for me. It was tested on 2 monitors, LG FLATRON L225WS 22" and a YAKUMO 17" for which more details are unknown. Signed-off-by: Pantelis Koukousoulas <pktoss@gmail.com> Signed-off-by: Dave Airlie <airlied@redhat.com>
203 lines
5.2 KiB
C
203 lines
5.2 KiB
C
/*
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* Copyright © 2007-2008 Intel Corporation
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* Jesse Barnes <jesse.barnes@intel.com>
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
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* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
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* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
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* OTHER DEALINGS IN THE SOFTWARE.
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*/
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#ifndef __DRM_EDID_H__
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#define __DRM_EDID_H__
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#include <linux/types.h>
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#define EDID_LENGTH 128
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#define DDC_ADDR 0x50
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#ifdef BIG_ENDIAN
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#error "EDID structure is little endian, need big endian versions"
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#else
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struct est_timings {
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u8 t1;
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u8 t2;
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u8 mfg_rsvd;
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} __attribute__((packed));
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struct std_timing {
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u8 hsize; /* need to multiply by 8 then add 248 */
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u8 vfreq:6; /* need to add 60 */
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u8 aspect_ratio:2; /* 00=16:10, 01=4:3, 10=5:4, 11=16:9 */
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} __attribute__((packed));
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/* If detailed data is pixel timing */
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struct detailed_pixel_timing {
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u8 hactive_lo;
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u8 hblank_lo;
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u8 hblank_hi:4;
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u8 hactive_hi:4;
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u8 vactive_lo;
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u8 vblank_lo;
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u8 vblank_hi:4;
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u8 vactive_hi:4;
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u8 hsync_offset_lo;
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u8 hsync_pulse_width_lo;
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u8 vsync_pulse_width_lo:4;
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u8 vsync_offset_lo:4;
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u8 vsync_pulse_width_hi:2;
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u8 vsync_offset_hi:2;
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u8 hsync_pulse_width_hi:2;
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u8 hsync_offset_hi:2;
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u8 width_mm_lo;
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u8 height_mm_lo;
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u8 height_mm_hi:4;
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u8 width_mm_hi:4;
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u8 hborder;
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u8 vborder;
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u8 unknown0:1;
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u8 hsync_positive:1;
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u8 vsync_positive:1;
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u8 separate_sync:2;
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u8 stereo:1;
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u8 unknown6:1;
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u8 interlaced:1;
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} __attribute__((packed));
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/* If it's not pixel timing, it'll be one of the below */
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struct detailed_data_string {
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u8 str[13];
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} __attribute__((packed));
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struct detailed_data_monitor_range {
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u8 min_vfreq;
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u8 max_vfreq;
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u8 min_hfreq_khz;
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u8 max_hfreq_khz;
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u8 pixel_clock_mhz; /* need to multiply by 10 */
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u16 sec_gtf_toggle; /* A000=use above, 20=use below */ /* FIXME: byte order */
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u8 hfreq_start_khz; /* need to multiply by 2 */
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u8 c; /* need to divide by 2 */
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u16 m; /* FIXME: byte order */
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u8 k;
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u8 j; /* need to divide by 2 */
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} __attribute__((packed));
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struct detailed_data_wpindex {
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u8 white_y_lo:2;
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u8 white_x_lo:2;
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u8 pad:4;
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u8 white_x_hi;
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u8 white_y_hi;
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u8 gamma; /* need to divide by 100 then add 1 */
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} __attribute__((packed));
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struct detailed_data_color_point {
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u8 windex1;
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u8 wpindex1[3];
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u8 windex2;
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u8 wpindex2[3];
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} __attribute__((packed));
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struct detailed_non_pixel {
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u8 pad1;
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u8 type; /* ff=serial, fe=string, fd=monitor range, fc=monitor name
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fb=color point data, fa=standard timing data,
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f9=undefined, f8=mfg. reserved */
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u8 pad2;
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union {
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struct detailed_data_string str;
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struct detailed_data_monitor_range range;
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struct detailed_data_wpindex color;
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struct std_timing timings[5];
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} data;
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} __attribute__((packed));
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#define EDID_DETAIL_STD_MODES 0xfa
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#define EDID_DETAIL_MONITOR_CPDATA 0xfb
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#define EDID_DETAIL_MONITOR_NAME 0xfc
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#define EDID_DETAIL_MONITOR_RANGE 0xfd
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#define EDID_DETAIL_MONITOR_STRING 0xfe
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#define EDID_DETAIL_MONITOR_SERIAL 0xff
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struct detailed_timing {
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u16 pixel_clock; /* need to multiply by 10 KHz */ /* FIXME: byte order */
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union {
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struct detailed_pixel_timing pixel_data;
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struct detailed_non_pixel other_data;
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} data;
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} __attribute__((packed));
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struct edid {
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u8 header[8];
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/* Vendor & product info */
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u8 mfg_id[2];
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u8 prod_code[2];
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u32 serial; /* FIXME: byte order */
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u8 mfg_week;
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u8 mfg_year;
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/* EDID version */
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u8 version;
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u8 revision;
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/* Display info: */
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/* input definition */
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u8 serration_vsync:1;
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u8 sync_on_green:1;
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u8 composite_sync:1;
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u8 separate_syncs:1;
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u8 blank_to_black:1;
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u8 video_level:2;
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u8 digital:1; /* bits below must be zero if set */
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u8 width_cm;
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u8 height_cm;
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u8 gamma;
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/* feature support */
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u8 default_gtf:1;
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u8 preferred_timing:1;
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u8 standard_color:1;
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u8 display_type:2; /* 00=mono, 01=rgb, 10=non-rgb, 11=unknown */
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u8 pm_active_off:1;
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u8 pm_suspend:1;
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u8 pm_standby:1;
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/* Color characteristics */
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u8 red_green_lo;
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u8 black_white_lo;
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u8 red_x;
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u8 red_y;
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u8 green_x;
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u8 green_y;
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u8 blue_x;
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u8 blue_y;
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u8 white_x;
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u8 white_y;
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/* Est. timings and mfg rsvd timings*/
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struct est_timings established_timings;
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/* Standard timings 1-8*/
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struct std_timing standard_timings[8];
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/* Detailing timings 1-4 */
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struct detailed_timing detailed_timings[4];
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/* Number of 128 byte ext. blocks */
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u8 extensions;
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/* Checksum */
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u8 checksum;
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} __attribute__((packed));
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#endif /* little endian structs */
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#define EDID_PRODUCT_ID(e) ((e)->prod_code[0] | ((e)->prod_code[1] << 8))
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#endif /* __DRM_EDID_H__ */
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