mirror of
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2ec98f5678
Core: - When a gpio_chip request GPIOs from itself, it can now fully control the line characteristics, both machine and consumer flags. This makes a lot of sense, but took some time before I figured out that this is how it has to work. - Several smallish documentation fixes. New drivers: - The PCA953x driver now supports the TI TCA9539. - The DaVinci driver now supports the K3 AM654 SoCs. Driver improvements: - Major overhaul and hardening of the OMAP driver by Russell King. - Starting to move some drivers to the new API passing irq_chip along with the gpio_chip when adding the gpio_chip instead of adding it separately. Unrelated: - Delete the FMC subsystem. -----BEGIN PGP SIGNATURE----- iQIzBAABCAAdFiEElDRnuGcz/wPCXQWMQRCzN7AZXXMFAl0i7gEACgkQQRCzN7AZ XXOeUA/+JKyI2zebTWBcgtxhn6VQCufMCtFmQl2JkEcy4pT7aBJcGWqFQCBW2Szf VTtqc8nNa90SZoOzsNbkeQgRjNKGZruMbh0ARUPcW4v3ZJHtUNUEDLTo8c3iyTgS 9k/FTeaTLt4WSZujeAO0O7G4KNnOOlTKLh58dr0PmXUR+0v+fbMhcJqJ9ABueV+V qENdpkTuG1ZcvzgLhBBEXdt3Plw9ICLWmPXtwY+784ewucVPbyQX7jV4+bBZ25fL DerCuMIgL5vRWWdiFO6/Jp603rHzZpTnjLJJocXUFiD6zA5rvU2jTWxsnUttjisg 8cTLMyQspsDvBxhEhCJVTuIKotbKH900TSaz+vx20W72/A1euy4y6uVi8FGZo4Ww KDkzB7anwHyEFKGnlYgHzDrfctgZrhQoyFz808DQRYg1JseZB5oGVDvScrPBD43j nbNDd8gwG4yp3tFnDx9xjIwQy3Ax4d510rAZyUN2801IlbA1bueq4t6Z2cCucWzX XA1gCKlXe4BUeitRAoZtqZNZG1ymEysW4jXy1V8xrwtAf8+QSN+xO98akz3VpnQL ae9q+HtF76fDBY1xFSXT37Ma3+4OR2vMF9QWuo4TCb9j1cL7llf8ZxtUq9LEHbDu erKLSSnwSFmqJNGSEA5SulGOCR/tRPkClngE9x0XEM6gOD+bs6E= =8zSV -----END PGP SIGNATURE----- Merge tag 'gpio-v5.3-1' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-gpio Pull GPIO updates from Linus Walleij: "This is the big slew of GPIO changes for the v5.3 kernel cycle. This is mostly incremental work this time. Three important things: - The FMC subsystem is deleted through my tree. This happens through GPIO as its demise was discussed in relation to a patch decoupling its GPIO implementation from the standard way of handling GPIO. As it turns out, that is not the only subsystem it reimplements and the authors think it is better do scratch it and start over using the proper kernel subsystems than try to polish the rust shiny. See the commit (ACKed by the maintainers) for details. - Arnd made a small devres patch that was ACKed by Greg and goes into the device core. - SPDX header change colissions may happen, because at times I've seen that quite a lot changed during the -rc:s in regards to SPDX. (It is good stuff, tglx has me convinced, and it is worth the occasional pain.) Apart from this is is nothing controversial or problematic. Summary: Core: - When a gpio_chip request GPIOs from itself, it can now fully control the line characteristics, both machine and consumer flags. This makes a lot of sense, but took some time before I figured out that this is how it has to work. - Several smallish documentation fixes. New drivers: - The PCA953x driver now supports the TI TCA9539. - The DaVinci driver now supports the K3 AM654 SoCs. Driver improvements: - Major overhaul and hardening of the OMAP driver by Russell King. - Starting to move some drivers to the new API passing irq_chip along with the gpio_chip when adding the gpio_chip instead of adding it separately. Unrelated: - Delete the FMC subsystem" * tag 'gpio-v5.3-1' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-gpio: (87 commits) Revert "gpio: tegra: Clean-up debugfs initialisation" gpiolib: Use spinlock_t instead of struct spinlock gpio: stp-xway: allow compile-testing gpio: stp-xway: get rid of the #include <lantiq_soc.h> dependency gpio: stp-xway: improve module clock error handling gpio: stp-xway: simplify error handling in xway_stp_probe() gpiolib: Clarify use of non-sleeping functions gpiolib: Fix references to gpiod_[gs]et_*value_cansleep() variants gpiolib: Document new gpio_chip.init_valid_mask field Documentation: gpio: Fix reference to gpiod_get_array() gpio: pl061: drop duplicate printing of device name gpio: altera: Pass irqchip when adding gpiochip gpio: siox: Use devm_ managed gpiochip gpio: siox: Add struct device *dev helper variable gpio: siox: Pass irqchip when adding gpiochip drivers: gpio: amd-fch: make resource struct const devres: allow const resource arguments gpio: ath79: Pass irqchip when adding gpiochip gpio: tegra: Clean-up debugfs initialisation gpio: siox: Switch to IRQ_TYPE_NONE ...
317 lines
8.3 KiB
C
317 lines
8.3 KiB
C
// SPDX-License-Identifier: GPL-2.0-only
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/*
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* Atheros AR71XX/AR724X/AR913X GPIO API support
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*
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* Copyright (C) 2015 Alban Bedel <albeu@free.fr>
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* Copyright (C) 2010-2011 Jaiganesh Narayanan <jnarayanan@atheros.com>
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* Copyright (C) 2008-2011 Gabor Juhos <juhosg@openwrt.org>
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* Copyright (C) 2008 Imre Kaloz <kaloz@openwrt.org>
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*/
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#include <linux/gpio/driver.h>
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#include <linux/platform_data/gpio-ath79.h>
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#include <linux/of_device.h>
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#include <linux/interrupt.h>
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#include <linux/module.h>
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#include <linux/irq.h>
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#define AR71XX_GPIO_REG_OE 0x00
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#define AR71XX_GPIO_REG_IN 0x04
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#define AR71XX_GPIO_REG_SET 0x0c
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#define AR71XX_GPIO_REG_CLEAR 0x10
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#define AR71XX_GPIO_REG_INT_ENABLE 0x14
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#define AR71XX_GPIO_REG_INT_TYPE 0x18
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#define AR71XX_GPIO_REG_INT_POLARITY 0x1c
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#define AR71XX_GPIO_REG_INT_PENDING 0x20
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#define AR71XX_GPIO_REG_INT_MASK 0x24
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struct ath79_gpio_ctrl {
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struct gpio_chip gc;
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void __iomem *base;
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raw_spinlock_t lock;
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unsigned long both_edges;
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};
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static struct ath79_gpio_ctrl *irq_data_to_ath79_gpio(struct irq_data *data)
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{
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struct gpio_chip *gc = irq_data_get_irq_chip_data(data);
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return container_of(gc, struct ath79_gpio_ctrl, gc);
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}
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static u32 ath79_gpio_read(struct ath79_gpio_ctrl *ctrl, unsigned reg)
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{
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return readl(ctrl->base + reg);
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}
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static void ath79_gpio_write(struct ath79_gpio_ctrl *ctrl,
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unsigned reg, u32 val)
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{
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writel(val, ctrl->base + reg);
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}
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static bool ath79_gpio_update_bits(
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struct ath79_gpio_ctrl *ctrl, unsigned reg, u32 mask, u32 bits)
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{
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u32 old_val, new_val;
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old_val = ath79_gpio_read(ctrl, reg);
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new_val = (old_val & ~mask) | (bits & mask);
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if (new_val != old_val)
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ath79_gpio_write(ctrl, reg, new_val);
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return new_val != old_val;
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}
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static void ath79_gpio_irq_unmask(struct irq_data *data)
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{
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struct ath79_gpio_ctrl *ctrl = irq_data_to_ath79_gpio(data);
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u32 mask = BIT(irqd_to_hwirq(data));
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unsigned long flags;
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raw_spin_lock_irqsave(&ctrl->lock, flags);
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ath79_gpio_update_bits(ctrl, AR71XX_GPIO_REG_INT_MASK, mask, mask);
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raw_spin_unlock_irqrestore(&ctrl->lock, flags);
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}
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static void ath79_gpio_irq_mask(struct irq_data *data)
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{
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struct ath79_gpio_ctrl *ctrl = irq_data_to_ath79_gpio(data);
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u32 mask = BIT(irqd_to_hwirq(data));
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unsigned long flags;
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raw_spin_lock_irqsave(&ctrl->lock, flags);
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ath79_gpio_update_bits(ctrl, AR71XX_GPIO_REG_INT_MASK, mask, 0);
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raw_spin_unlock_irqrestore(&ctrl->lock, flags);
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}
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static void ath79_gpio_irq_enable(struct irq_data *data)
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{
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struct ath79_gpio_ctrl *ctrl = irq_data_to_ath79_gpio(data);
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u32 mask = BIT(irqd_to_hwirq(data));
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unsigned long flags;
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raw_spin_lock_irqsave(&ctrl->lock, flags);
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ath79_gpio_update_bits(ctrl, AR71XX_GPIO_REG_INT_ENABLE, mask, mask);
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ath79_gpio_update_bits(ctrl, AR71XX_GPIO_REG_INT_MASK, mask, mask);
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raw_spin_unlock_irqrestore(&ctrl->lock, flags);
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}
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static void ath79_gpio_irq_disable(struct irq_data *data)
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{
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struct ath79_gpio_ctrl *ctrl = irq_data_to_ath79_gpio(data);
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u32 mask = BIT(irqd_to_hwirq(data));
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unsigned long flags;
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raw_spin_lock_irqsave(&ctrl->lock, flags);
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ath79_gpio_update_bits(ctrl, AR71XX_GPIO_REG_INT_MASK, mask, 0);
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ath79_gpio_update_bits(ctrl, AR71XX_GPIO_REG_INT_ENABLE, mask, 0);
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raw_spin_unlock_irqrestore(&ctrl->lock, flags);
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}
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static int ath79_gpio_irq_set_type(struct irq_data *data,
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unsigned int flow_type)
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{
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struct ath79_gpio_ctrl *ctrl = irq_data_to_ath79_gpio(data);
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u32 mask = BIT(irqd_to_hwirq(data));
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u32 type = 0, polarity = 0;
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unsigned long flags;
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bool disabled;
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switch (flow_type) {
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case IRQ_TYPE_EDGE_RISING:
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polarity |= mask;
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case IRQ_TYPE_EDGE_FALLING:
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case IRQ_TYPE_EDGE_BOTH:
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break;
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case IRQ_TYPE_LEVEL_HIGH:
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polarity |= mask;
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/* fall through */
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case IRQ_TYPE_LEVEL_LOW:
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type |= mask;
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break;
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default:
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return -EINVAL;
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}
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raw_spin_lock_irqsave(&ctrl->lock, flags);
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if (flow_type == IRQ_TYPE_EDGE_BOTH) {
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ctrl->both_edges |= mask;
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polarity = ~ath79_gpio_read(ctrl, AR71XX_GPIO_REG_IN);
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} else {
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ctrl->both_edges &= ~mask;
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}
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/* As the IRQ configuration can't be loaded atomically we
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* have to disable the interrupt while the configuration state
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* is invalid.
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*/
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disabled = ath79_gpio_update_bits(
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ctrl, AR71XX_GPIO_REG_INT_ENABLE, mask, 0);
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ath79_gpio_update_bits(
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ctrl, AR71XX_GPIO_REG_INT_TYPE, mask, type);
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ath79_gpio_update_bits(
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ctrl, AR71XX_GPIO_REG_INT_POLARITY, mask, polarity);
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if (disabled)
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ath79_gpio_update_bits(
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ctrl, AR71XX_GPIO_REG_INT_ENABLE, mask, mask);
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raw_spin_unlock_irqrestore(&ctrl->lock, flags);
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return 0;
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}
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static struct irq_chip ath79_gpio_irqchip = {
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.name = "gpio-ath79",
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.irq_enable = ath79_gpio_irq_enable,
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.irq_disable = ath79_gpio_irq_disable,
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.irq_mask = ath79_gpio_irq_mask,
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.irq_unmask = ath79_gpio_irq_unmask,
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.irq_set_type = ath79_gpio_irq_set_type,
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};
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static void ath79_gpio_irq_handler(struct irq_desc *desc)
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{
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struct gpio_chip *gc = irq_desc_get_handler_data(desc);
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struct irq_chip *irqchip = irq_desc_get_chip(desc);
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struct ath79_gpio_ctrl *ctrl =
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container_of(gc, struct ath79_gpio_ctrl, gc);
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unsigned long flags, pending;
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u32 both_edges, state;
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int irq;
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chained_irq_enter(irqchip, desc);
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raw_spin_lock_irqsave(&ctrl->lock, flags);
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pending = ath79_gpio_read(ctrl, AR71XX_GPIO_REG_INT_PENDING);
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/* Update the polarity of the both edges irqs */
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both_edges = ctrl->both_edges & pending;
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if (both_edges) {
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state = ath79_gpio_read(ctrl, AR71XX_GPIO_REG_IN);
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ath79_gpio_update_bits(ctrl, AR71XX_GPIO_REG_INT_POLARITY,
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both_edges, ~state);
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}
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raw_spin_unlock_irqrestore(&ctrl->lock, flags);
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if (pending) {
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for_each_set_bit(irq, &pending, gc->ngpio)
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generic_handle_irq(
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irq_linear_revmap(gc->irq.domain, irq));
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}
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chained_irq_exit(irqchip, desc);
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}
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static const struct of_device_id ath79_gpio_of_match[] = {
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{ .compatible = "qca,ar7100-gpio" },
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{ .compatible = "qca,ar9340-gpio" },
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{},
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};
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MODULE_DEVICE_TABLE(of, ath79_gpio_of_match);
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static int ath79_gpio_probe(struct platform_device *pdev)
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{
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struct ath79_gpio_platform_data *pdata = dev_get_platdata(&pdev->dev);
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struct device *dev = &pdev->dev;
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struct device_node *np = dev->of_node;
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struct ath79_gpio_ctrl *ctrl;
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struct gpio_irq_chip *girq;
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struct resource *res;
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u32 ath79_gpio_count;
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bool oe_inverted;
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int err;
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ctrl = devm_kzalloc(dev, sizeof(*ctrl), GFP_KERNEL);
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if (!ctrl)
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return -ENOMEM;
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platform_set_drvdata(pdev, ctrl);
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if (np) {
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err = of_property_read_u32(np, "ngpios", &ath79_gpio_count);
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if (err) {
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dev_err(dev, "ngpios property is not valid\n");
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return err;
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}
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oe_inverted = of_device_is_compatible(np, "qca,ar9340-gpio");
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} else if (pdata) {
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ath79_gpio_count = pdata->ngpios;
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oe_inverted = pdata->oe_inverted;
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} else {
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dev_err(dev, "No DT node or platform data found\n");
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return -EINVAL;
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}
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if (ath79_gpio_count >= 32) {
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dev_err(dev, "ngpios must be less than 32\n");
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return -EINVAL;
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}
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res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
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if (!res)
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return -EINVAL;
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ctrl->base = devm_ioremap_nocache(dev, res->start, resource_size(res));
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if (!ctrl->base)
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return -ENOMEM;
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raw_spin_lock_init(&ctrl->lock);
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err = bgpio_init(&ctrl->gc, dev, 4,
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ctrl->base + AR71XX_GPIO_REG_IN,
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ctrl->base + AR71XX_GPIO_REG_SET,
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ctrl->base + AR71XX_GPIO_REG_CLEAR,
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oe_inverted ? NULL : ctrl->base + AR71XX_GPIO_REG_OE,
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oe_inverted ? ctrl->base + AR71XX_GPIO_REG_OE : NULL,
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0);
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if (err) {
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dev_err(dev, "bgpio_init failed\n");
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return err;
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}
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/* Use base 0 to stay compatible with legacy platforms */
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ctrl->gc.base = 0;
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/* Optional interrupt setup */
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if (!np || of_property_read_bool(np, "interrupt-controller")) {
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girq = &ctrl->gc.irq;
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girq->chip = &ath79_gpio_irqchip;
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girq->parent_handler = ath79_gpio_irq_handler;
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girq->num_parents = 1;
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girq->parents = devm_kcalloc(dev, 1, sizeof(*girq->parents),
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GFP_KERNEL);
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if (!girq->parents)
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return -ENOMEM;
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girq->parents[0] = platform_get_irq(pdev, 0);
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girq->default_type = IRQ_TYPE_NONE;
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girq->handler = handle_simple_irq;
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}
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err = devm_gpiochip_add_data(dev, &ctrl->gc, ctrl);
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if (err) {
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dev_err(dev,
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"cannot add AR71xx GPIO chip, error=%d", err);
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return err;
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}
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return 0;
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}
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static struct platform_driver ath79_gpio_driver = {
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.driver = {
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.name = "ath79-gpio",
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.of_match_table = ath79_gpio_of_match,
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},
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.probe = ath79_gpio_probe,
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};
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module_platform_driver(ath79_gpio_driver);
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MODULE_DESCRIPTION("Atheros AR71XX/AR724X/AR913X GPIO API support");
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MODULE_LICENSE("GPL v2");
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