Luke Nelson 073ca6a036 bpf, riscv: Optimize BPF_JSET BPF_K using andi on RV64 ... This patch optimizes BPF_JSET BPF_K by using a RISC-V andi instruction when the BPF immediate fits in 12 bits, instead of first loading the immediate to a temporary register. Examples of generated code with and without this optimization: BPF_JMP_IMM(BPF_JSET, R1, 2, 1) without optimization: 20: li t1,2 24: and t1,a0,t1 28: bnez t1,0x30 BPF_JMP_IMM(BPF_JSET, R1, 2, 1) with optimization: 20: andi t1,a0,2 24: bnez t1,0x2c BPF_JMP32_IMM(BPF_JSET, R1, 2, 1) without optimization: 20: li t1,2 24: mv t2,a0 28: slli t2,t2,0x20 2c: srli t2,t2,0x20 30: slli t1,t1,0x20 34: srli t1,t1,0x20 38: and t1,t2,t1 3c: bnez t1,0x44 BPF_JMP32_IMM(BPF_JSET, R1, 2, 1) with optimization: 20: andi t1,a0,2 24: bnez t1,0x2c In these examples, because the upper 32 bits of the sign-extended immediate are 0, BPF_JMP BPF_JSET and BPF_JMP32 BPF_JSET are equivalent and therefore the JIT produces identical code for them. Co-developed-by: Xi Wang <xi.wang@gmail.com> Signed-off-by: Xi Wang <xi.wang@gmail.com> Signed-off-by: Luke Nelson <luke.r.nels@gmail.com> Signed-off-by: Daniel Borkmann <daniel@iogearbox.net> Reviewed-by: Björn Töpel <bjorn.topel@gmail.com> Acked-by: Björn Töpel <bjorn.topel@gmail.com> Link: https://lore.kernel.org/bpf/20200506000320.28965-5-luke.r.nels@gmail.com		2020-05-06 09:48:15 +02:00
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bpf_jit_comp32.c	bpf, riscv: Fix stack layout of JITed code on RV32	2020-04-30 16:14:50 +02:00
bpf_jit_comp64.c	bpf, riscv: Optimize BPF_JSET BPF_K using andi on RV64	2020-05-06 09:48:15 +02:00
bpf_jit_core.c	riscv, bpf: Factor common RISC-V JIT code	2020-03-05 16:13:47 +01:00
bpf_jit.h	riscv, bpf: Add RV32G eBPF JIT	2020-03-05 16:13:47 +01:00
Makefile	riscv, bpf: Add RV32G eBPF JIT	2020-03-05 16:13:47 +01:00