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* A pair of device tree fixes for the Polarfire SOC. * A fix to avoid overflowing the PMU counter array when firmware incorrectly reports the number of supported counters, which manifests on OpenSBI versions prior to 1.1. -----BEGIN PGP SIGNATURE----- iQJHBAABCAAxFiEEKzw3R0RoQ7JKlDp6LhMZ81+7GIkFAmMbRnQTHHBhbG1lckBk YWJiZWx0LmNvbQAKCRAuExnzX7sYiU1YEADJTiBZwv7C4yrDIBtVolTuNhO1IT5U Y9h4iWeJcg08oHoBJCCy731zd56/Kaiqoje99ou/G+wzs4Idze9dgElrFQY2bOE+ JPCnJ6Vcc/F7jjrZfJziAyP3QxdSIVebljKynaRyzkCxCNbL7QI26PrdmqpaXPQv orpk4kZFdAzEK9SBnYL2L5cPn3387N9l+F7RcunmAM61L+YkPXKSftK5JDK9wv/6 W7RjxODbNni7dRIZsGTjFUEnR60UKsAiCvzA3IszWIRJcPTkPULhvpO8M67Z87qa DLq1zx0dn+ZLBb2prn/9UHHpqJFgoi7nuvoaGtqnMuCUIADkuRGW/y7ZNaSb+KIK j0c4hDrQ/if7UhXVnWc8EHmsOhaLKBXh9f4NGL9CjSDOw8K3RvC1GvKr+g8jMah+ 5Gi8KfbMLK5z4IK2jzJZe7tYY5YcgieG/M7HCnZo7O3A9ao84DXSjSUXgU4sfYI5 QeYO5A51xOA7ZlsKrK0hxOfGcZf1uwXA/ZyPTPloSRmVL42Ji1V1rgSGO6I4A493 SUZEQ3nrEmmOemf8pE5t65IIRNQ3/sPWLZRqoBgtRn8pUJ0TqTxX+VPFAEAuGFqB g5LDr77+ek2kQSw1PU9wZmi/3WUpB0WhVCDJQgdc8RgZP9vOdUc9oh5gq+T2he+K 17NsZsP+LrmMUQ== =86+k -----END PGP SIGNATURE----- Merge tag 'riscv-for-linus-6.0-rc5' of git://git.kernel.org/pub/scm/linux/kernel/git/riscv/linux Pull RISC-V fixes from Palmer Dabbelt: - A pair of device tree fixes for the Polarfire SOC - A fix to avoid overflowing the PMU counter array when firmware incorrectly reports the number of supported counters, which manifests on OpenSBI versions prior to 1.1 * tag 'riscv-for-linus-6.0-rc5' of git://git.kernel.org/pub/scm/linux/kernel/git/riscv/linux: perf: RISC-V: fix access beyond allocated array riscv: dts: microchip: use an mpfs specific l2 compatible dt-bindings: riscv: sifive-l2: add a PolarFire SoC compatible |
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.. | ||
hisilicon | ||
apple_m1_cpu_pmu.c | ||
arm_dmc620_pmu.c | ||
arm_dsu_pmu.c | ||
arm_pmu_acpi.c | ||
arm_pmu_platform.c | ||
arm_pmu.c | ||
arm_smmuv3_pmu.c | ||
arm_spe_pmu.c | ||
arm-cci.c | ||
arm-ccn.c | ||
arm-cmn.c | ||
fsl_imx8_ddr_perf.c | ||
Kconfig | ||
Makefile | ||
marvell_cn10k_ddr_pmu.c | ||
marvell_cn10k_tad_pmu.c | ||
qcom_l2_pmu.c | ||
qcom_l3_pmu.c | ||
riscv_pmu_legacy.c | ||
riscv_pmu_sbi.c | ||
riscv_pmu.c | ||
thunderx2_pmu.c | ||
xgene_pmu.c |