mirror of
https://github.com/torvalds/linux.git
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f991fae5c6
- Hotplug changes allowing device hot-removal operations to fail gracefully (instead of crashing the kernel) if they cannot be carried out completely. From Rafael J Wysocki and Toshi Kani. - Freezer update from Colin Cross and Mandeep Singh Baines targeted at making the freezing of tasks a bit less heavy weight operation. - cpufreq resume fix from Srivatsa S Bhat for a regression introduced during the 3.10 cycle causing some cpufreq sysfs attributes to return wrong values to user space after resume. - New freqdomain_cpus sysfs attribute for the acpi-cpufreq driver to provide information previously available via related_cpus from Lan Tianyu. - cpufreq fixes and cleanups from Viresh Kumar, Jacob Shin, Heiko Stübner, Xiaoguang Chen, Ezequiel Garcia, Arnd Bergmann, and Tang Yuantian. - Fix for an ACPICA regression causing suspend/resume issues to appear on some systems introduced during the 3.4 development cycle from Lv Zheng. - ACPICA fixes and cleanups from Bob Moore, Tomasz Nowicki, Lv Zheng, Chao Guan, and Zhang Rui. - New cupidle driver for Xilinx Zynq processors from Michal Simek. - cpuidle fixes and cleanups from Daniel Lezcano. - Changes to make suspend/resume work correctly in Xen guests from Konrad Rzeszutek Wilk. - ACPI device power management fixes and cleanups from Fengguang Wu and Rafael J Wysocki. - ACPI documentation updates from Lv Zheng, Aaron Lu and Hanjun Guo. - Fix for the IA-64 issue that was the reason for reverting commit9f29ab1
and updates of the ACPI scan code from Rafael J Wysocki. - Mechanism for adding CMOS RTC address space handlers from Lan Tianyu (to allow some EC-related breakage to be fixed on some systems). - Spec-compliant implementation of acpi_os_get_timer() from Mika Westerberg. - Modification of do_acpi_find_child() to execute _STA in order to to avoid situations in which a pointer to a disabled device object is returned instead of an enabled one with the same _ADR value. From Jeff Wu. - Intel BayTrail PCH (Platform Controller Hub) support for the ACPI Intel Low-Power Subsystems (LPSS) driver and modificaions of that driver to work around a couple of known BIOS issues from Mika Westerberg and Heikki Krogerus. - EC driver fix from Vasiliy Kulikov to make it use get_user() and put_user() instead of dereferencing user space pointers blindly. - Assorted ACPI code cleanups from Bjorn Helgaas, Nicholas Mazzuca and Toshi Kani. - Modification of the "runtime idle" helper routine to take the return values of the callbacks executed by it into account and to call rpm_suspend() if they return 0, which allows some code bloat reduction to be done, from Rafael J Wysocki and Alan Stern. - New trace points for PM QoS from Sahara <keun-o.park@windriver.com>. - PM QoS documentation update from Lan Tianyu. - Assorted core PM code cleanups and changes from Bernie Thompson, Bjorn Helgaas, Julius Werner, and Shuah Khan. - New devfreq driver for the Exynos5-bus device from Abhilash Kesavan. - Minor devfreq cleanups, fixes and MAINTAINERS update from MyungJoo Ham, Abhilash Kesavan, Paul Bolle, Rajagopal Venkat, and Wei Yongjun. - OMAP Adaptive Voltage Scaling (AVS) SmartReflex voltage control driver updates from Andrii Tseglytskyi and Nishanth Menon. / -----BEGIN PGP SIGNATURE----- Version: GnuPG v2.0.19 (GNU/Linux) iQIcBAABAgAGBQJR0ZNOAAoJEKhOf7ml8uNsDLYP/0EU4rmvw0TWTITfp6RS1KDE 9GwBn96ZR4Q5bJd9gBCTPSqhHOYMqxWEUp99sn/M2wehG1pk/jw5LO56+2IhM3UZ g1HDcJ7te2nVT/iXsKiAGTVhU9Rk0aYwoVSknwk27qpIBGxW9w/s5tLX8pY3Q3Zq wL/7aTPjyL+PFFFEaxgH7qLqsl3DhbtYW5AriUBTkXout/tJ4eO1b7MNBncLDh8X VQ/0DNCKE95VEJfkO4rk9RKUyVp9GDn0i+HXCD/FS4IA5oYzePdVdNDmXf7g+swe CGlTZq8pB+oBpDiHl4lxzbNrKQjRNbGnDUkoRcWqn0nAw56xK+vmYnWJhW99gQ/I fKnvxeLca5po1aiqmC4VSJxZIatFZqLrZAI4dzoCLWY+bGeTnCKmj0/F8ytFnZA2 8IuLLs7/dFOaHXV/pKmpg6FAlFa9CPxoqRFoyqb4M0GjEarADyalXUWsPtG+6xCp R/p0CISpwk+guKZR/qPhL7M654S7SHrPwd2DPF0KgGsvk+G2GhoB8EzvD8BVp98Z 9siCGCdgKQfJQVI6R0k9aFmn/4gRQIAgyPhkhv9tqULUUkiaXki+/t8kPfnb8O/d zep+CA57E2G8MYLkDJfpFeKS7GpPD6TIdgFdGmOUC0Y6sl9iTdiw4yTx8O2JM37z rHBZfYGkJBrbGRu+Q1gs =VBBq -----END PGP SIGNATURE----- Merge tag 'pm+acpi-3.11-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/rafael/linux-pm Pull power management and ACPI updates from Rafael Wysocki: "This time the total number of ACPI commits is slightly greater than the number of cpufreq commits, but Viresh Kumar (who works on cpufreq) remains the most active patch submitter. To me, the most significant change is the addition of offline/online device operations to the driver core (with the Greg's blessing) and the related modifications of the ACPI core hotplug code. Next are the freezer updates from Colin Cross that should make the freezing of tasks a bit less heavy weight. We also have a couple of regression fixes, a number of fixes for issues that have not been identified as regressions, two new drivers and a bunch of cleanups all over. Highlights: - Hotplug changes to support graceful hot-removal failures. It sometimes is necessary to fail device hot-removal operations gracefully if they cannot be carried out completely. For example, if memory from a memory module being hot-removed has been allocated for the kernel's own use and cannot be moved elsewhere, it's desirable to fail the hot-removal operation in a graceful way rather than to crash the kernel, but currenty a success or a kernel crash are the only possible outcomes of an attempted memory hot-removal. Needless to say, that is not a very attractive alternative and it had to be addressed. However, in order to make it work for memory, I first had to make it work for CPUs and for this purpose I needed to modify the ACPI processor driver. It's been split into two parts, a resident one handling the low-level initialization/cleanup and a modular one playing the actual driver's role (but it binds to the CPU system device objects rather than to the ACPI device objects representing processors). That's been sort of like a live brain surgery on a patient who's riding a bike. So this is a little scary, but since we found and fixed a couple of regressions it caused to happen during the early linux-next testing (a month ago), nobody has complained. As a bonus we remove some duplicated ACPI hotplug code, because the ACPI-based CPU hotplug is now going to use the common ACPI hotplug code. - Lighter weight freezing of tasks. These changes from Colin Cross and Mandeep Singh Baines are targeted at making the freezing of tasks a bit less heavy weight operation. They reduce the number of tasks woken up every time during the freezing, by using the observation that the freezer simply doesn't need to wake up some of them and wait for them all to call refrigerator(). The time needed for the freezer to decide to report a failure is reduced too. Also reintroduced is the check causing a lockdep warining to trigger when try_to_freeze() is called with locks held (which is generally unsafe and shouldn't happen). - cpufreq updates First off, a commit from Srivatsa S Bhat fixes a resume regression introduced during the 3.10 cycle causing some cpufreq sysfs attributes to return wrong values to user space after resume. The fix is kind of fresh, but also it's pretty obvious once Srivatsa has identified the root cause. Second, we have a new freqdomain_cpus sysfs attribute for the acpi-cpufreq driver to provide information previously available via related_cpus. From Lan Tianyu. Finally, we fix a number of issues, mostly related to the CPUFREQ_POSTCHANGE notifier and cpufreq Kconfig options and clean up some code. The majority of changes from Viresh Kumar with bits from Jacob Shin, Heiko Stübner, Xiaoguang Chen, Ezequiel Garcia, Arnd Bergmann, and Tang Yuantian. - ACPICA update A usual bunch of updates from the ACPICA upstream. During the 3.4 cycle we introduced support for ACPI 5 extended sleep registers, but they are only supposed to be used if the HW-reduced mode bit is set in the FADT flags and the code attempted to use them without checking that bit. That caused suspend/resume regressions to happen on some systems. Fix from Lv Zheng causes those registers to be used only if the HW-reduced mode bit is set. Apart from this some other ACPICA bugs are fixed and code cleanups are made by Bob Moore, Tomasz Nowicki, Lv Zheng, Chao Guan, and Zhang Rui. - cpuidle updates New driver for Xilinx Zynq processors is added by Michal Simek. Multidriver support simplification, addition of some missing kerneldoc comments and Kconfig-related fixes come from Daniel Lezcano. - ACPI power management updates Changes to make suspend/resume work correctly in Xen guests from Konrad Rzeszutek Wilk, sparse warning fix from Fengguang Wu and cleanups and fixes of the ACPI device power state selection routine. - ACPI documentation updates Some previously missing pieces of ACPI documentation are added by Lv Zheng and Aaron Lu (hopefully, that will help people to uderstand how the ACPI subsystem works) and one outdated doc is updated by Hanjun Guo. - Assorted ACPI updates We finally nailed down the IA-64 issue that was the reason for reverting commit9f29ab11dd
("ACPI / scan: do not match drivers against objects having scan handlers"), so we can fix it and move the ACPI scan handler check added to the ACPI video driver back to the core. A mechanism for adding CMOS RTC address space handlers is introduced by Lan Tianyu to allow some EC-related breakage to be fixed on some systems. A spec-compliant implementation of acpi_os_get_timer() is added by Mika Westerberg. The evaluation of _STA is added to do_acpi_find_child() to avoid situations in which a pointer to a disabled device object is returned instead of an enabled one with the same _ADR value. From Jeff Wu. Intel BayTrail PCH (Platform Controller Hub) support is added to the ACPI driver for Intel Low-Power Subsystems (LPSS) and that driver is modified to work around a couple of known BIOS issues. Changes from Mika Westerberg and Heikki Krogerus. The EC driver is fixed by Vasiliy Kulikov to use get_user() and put_user() instead of dereferencing user space pointers blindly. Code cleanups are made by Bjorn Helgaas, Nicholas Mazzuca and Toshi Kani. - Assorted power management updates The "runtime idle" helper routine is changed to take the return values of the callbacks executed by it into account and to call rpm_suspend() if they return 0, which allows us to reduce the overall code bloat a bit (by dropping some code that's not necessary any more after that modification). The runtime PM documentation is updated by Alan Stern (to reflect the "runtime idle" behavior change). New trace points for PM QoS are added by Sahara (<keun-o.park@windriver.com>). PM QoS documentation is updated by Lan Tianyu. Code cleanups are made and minor issues are addressed by Bernie Thompson, Bjorn Helgaas, Julius Werner, and Shuah Khan. - devfreq updates New driver for the Exynos5-bus device from Abhilash Kesavan. Minor cleanups, fixes and MAINTAINERS update from MyungJoo Ham, Abhilash Kesavan, Paul Bolle, Rajagopal Venkat, and Wei Yongjun. - OMAP power management updates Adaptive Voltage Scaling (AVS) SmartReflex voltage control driver updates from Andrii Tseglytskyi and Nishanth Menon." * tag 'pm+acpi-3.11-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/rafael/linux-pm: (162 commits) cpufreq: Fix cpufreq regression after suspend/resume ACPI / PM: Fix possible NULL pointer deref in acpi_pm_device_sleep_state() PM / Sleep: Warn about system time after resume with pm_trace cpufreq: don't leave stale policy pointer in cdbs->cur_policy acpi-cpufreq: Add new sysfs attribute freqdomain_cpus cpufreq: make sure frequency transitions are serialized ACPI: implement acpi_os_get_timer() according the spec ACPI / EC: Add HP Folio 13 to ec_dmi_table in order to skip DSDT scan ACPI: Add CMOS RTC Operation Region handler support ACPI / processor: Drop unused variable from processor_perflib.c cpufreq: tegra: call CPUFREQ_POSTCHANGE notfier in error cases cpufreq: s3c64xx: call CPUFREQ_POSTCHANGE notfier in error cases cpufreq: omap: call CPUFREQ_POSTCHANGE notfier in error cases cpufreq: imx6q: call CPUFREQ_POSTCHANGE notfier in error cases cpufreq: exynos: call CPUFREQ_POSTCHANGE notfier in error cases cpufreq: dbx500: call CPUFREQ_POSTCHANGE notfier in error cases cpufreq: davinci: call CPUFREQ_POSTCHANGE notfier in error cases cpufreq: arm-big-little: call CPUFREQ_POSTCHANGE notfier in error cases cpufreq: powernow-k8: call CPUFREQ_POSTCHANGE notfier in error cases cpufreq: pcc: call CPUFREQ_POSTCHANGE notfier in error cases ...
398 lines
9.9 KiB
C
398 lines
9.9 KiB
C
/*
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* Moorestown platform Langwell chip GPIO driver
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*
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* Copyright (c) 2008, 2009, 2013, Intel Corporation.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
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*/
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/* Supports:
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* Moorestown platform Langwell chip.
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* Medfield platform Penwell chip.
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*/
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#include <linux/module.h>
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#include <linux/pci.h>
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#include <linux/platform_device.h>
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#include <linux/kernel.h>
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#include <linux/delay.h>
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#include <linux/stddef.h>
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#include <linux/interrupt.h>
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#include <linux/init.h>
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#include <linux/irq.h>
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#include <linux/io.h>
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#include <linux/gpio.h>
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#include <linux/slab.h>
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#include <linux/pm_runtime.h>
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#include <linux/irqdomain.h>
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/*
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* Langwell chip has 64 pins and thus there are 2 32bit registers to control
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* each feature, while Penwell chip has 96 pins for each block, and need 3 32bit
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* registers to control them, so we only define the order here instead of a
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* structure, to get a bit offset for a pin (use GPDR as an example):
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*
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* nreg = ngpio / 32;
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* reg = offset / 32;
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* bit = offset % 32;
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* reg_addr = reg_base + GPDR * nreg * 4 + reg * 4;
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*
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* so the bit of reg_addr is to control pin offset's GPDR feature
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*/
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enum GPIO_REG {
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GPLR = 0, /* pin level read-only */
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GPDR, /* pin direction */
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GPSR, /* pin set */
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GPCR, /* pin clear */
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GRER, /* rising edge detect */
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GFER, /* falling edge detect */
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GEDR, /* edge detect result */
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GAFR, /* alt function */
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};
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struct lnw_gpio {
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struct gpio_chip chip;
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void __iomem *reg_base;
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spinlock_t lock;
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struct pci_dev *pdev;
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struct irq_domain *domain;
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};
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#define to_lnw_priv(chip) container_of(chip, struct lnw_gpio, chip)
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static void __iomem *gpio_reg(struct gpio_chip *chip, unsigned offset,
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enum GPIO_REG reg_type)
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{
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struct lnw_gpio *lnw = to_lnw_priv(chip);
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unsigned nreg = chip->ngpio / 32;
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u8 reg = offset / 32;
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return lnw->reg_base + reg_type * nreg * 4 + reg * 4;
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}
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static void __iomem *gpio_reg_2bit(struct gpio_chip *chip, unsigned offset,
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enum GPIO_REG reg_type)
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{
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struct lnw_gpio *lnw = to_lnw_priv(chip);
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unsigned nreg = chip->ngpio / 32;
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u8 reg = offset / 16;
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return lnw->reg_base + reg_type * nreg * 4 + reg * 4;
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}
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static int lnw_gpio_request(struct gpio_chip *chip, unsigned offset)
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{
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void __iomem *gafr = gpio_reg_2bit(chip, offset, GAFR);
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u32 value = readl(gafr);
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int shift = (offset % 16) << 1, af = (value >> shift) & 3;
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if (af) {
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value &= ~(3 << shift);
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writel(value, gafr);
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}
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return 0;
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}
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static int lnw_gpio_get(struct gpio_chip *chip, unsigned offset)
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{
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void __iomem *gplr = gpio_reg(chip, offset, GPLR);
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return readl(gplr) & BIT(offset % 32);
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}
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static void lnw_gpio_set(struct gpio_chip *chip, unsigned offset, int value)
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{
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void __iomem *gpsr, *gpcr;
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if (value) {
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gpsr = gpio_reg(chip, offset, GPSR);
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writel(BIT(offset % 32), gpsr);
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} else {
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gpcr = gpio_reg(chip, offset, GPCR);
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writel(BIT(offset % 32), gpcr);
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}
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}
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static int lnw_gpio_direction_input(struct gpio_chip *chip, unsigned offset)
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{
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struct lnw_gpio *lnw = to_lnw_priv(chip);
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void __iomem *gpdr = gpio_reg(chip, offset, GPDR);
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u32 value;
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unsigned long flags;
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if (lnw->pdev)
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pm_runtime_get(&lnw->pdev->dev);
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spin_lock_irqsave(&lnw->lock, flags);
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value = readl(gpdr);
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value &= ~BIT(offset % 32);
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writel(value, gpdr);
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spin_unlock_irqrestore(&lnw->lock, flags);
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if (lnw->pdev)
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pm_runtime_put(&lnw->pdev->dev);
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return 0;
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}
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static int lnw_gpio_direction_output(struct gpio_chip *chip,
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unsigned offset, int value)
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{
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struct lnw_gpio *lnw = to_lnw_priv(chip);
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void __iomem *gpdr = gpio_reg(chip, offset, GPDR);
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unsigned long flags;
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lnw_gpio_set(chip, offset, value);
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if (lnw->pdev)
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pm_runtime_get(&lnw->pdev->dev);
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spin_lock_irqsave(&lnw->lock, flags);
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value = readl(gpdr);
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value |= BIT(offset % 32);
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writel(value, gpdr);
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spin_unlock_irqrestore(&lnw->lock, flags);
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if (lnw->pdev)
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pm_runtime_put(&lnw->pdev->dev);
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return 0;
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}
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static int lnw_gpio_to_irq(struct gpio_chip *chip, unsigned offset)
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{
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struct lnw_gpio *lnw = to_lnw_priv(chip);
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return irq_create_mapping(lnw->domain, offset);
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}
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static int lnw_irq_type(struct irq_data *d, unsigned type)
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{
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struct lnw_gpio *lnw = irq_data_get_irq_chip_data(d);
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u32 gpio = irqd_to_hwirq(d);
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unsigned long flags;
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u32 value;
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void __iomem *grer = gpio_reg(&lnw->chip, gpio, GRER);
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void __iomem *gfer = gpio_reg(&lnw->chip, gpio, GFER);
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if (gpio >= lnw->chip.ngpio)
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return -EINVAL;
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if (lnw->pdev)
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pm_runtime_get(&lnw->pdev->dev);
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spin_lock_irqsave(&lnw->lock, flags);
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if (type & IRQ_TYPE_EDGE_RISING)
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value = readl(grer) | BIT(gpio % 32);
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else
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value = readl(grer) & (~BIT(gpio % 32));
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writel(value, grer);
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if (type & IRQ_TYPE_EDGE_FALLING)
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value = readl(gfer) | BIT(gpio % 32);
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else
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value = readl(gfer) & (~BIT(gpio % 32));
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writel(value, gfer);
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spin_unlock_irqrestore(&lnw->lock, flags);
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if (lnw->pdev)
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pm_runtime_put(&lnw->pdev->dev);
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return 0;
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}
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static void lnw_irq_unmask(struct irq_data *d)
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{
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}
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static void lnw_irq_mask(struct irq_data *d)
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{
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}
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static struct irq_chip lnw_irqchip = {
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.name = "LNW-GPIO",
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.irq_mask = lnw_irq_mask,
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.irq_unmask = lnw_irq_unmask,
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.irq_set_type = lnw_irq_type,
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};
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static DEFINE_PCI_DEVICE_TABLE(lnw_gpio_ids) = { /* pin number */
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{ PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x080f), .driver_data = 64 },
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{ PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x081f), .driver_data = 96 },
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{ PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x081a), .driver_data = 96 },
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{ PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x08eb), .driver_data = 96 },
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{ PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x08f7), .driver_data = 96 },
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{ 0, }
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};
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MODULE_DEVICE_TABLE(pci, lnw_gpio_ids);
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static void lnw_irq_handler(unsigned irq, struct irq_desc *desc)
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{
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struct irq_data *data = irq_desc_get_irq_data(desc);
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struct lnw_gpio *lnw = irq_data_get_irq_handler_data(data);
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struct irq_chip *chip = irq_data_get_irq_chip(data);
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u32 base, gpio, mask;
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unsigned long pending;
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void __iomem *gedr;
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/* check GPIO controller to check which pin triggered the interrupt */
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for (base = 0; base < lnw->chip.ngpio; base += 32) {
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gedr = gpio_reg(&lnw->chip, base, GEDR);
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while ((pending = readl(gedr))) {
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gpio = __ffs(pending);
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mask = BIT(gpio);
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/* Clear before handling so we can't lose an edge */
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writel(mask, gedr);
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generic_handle_irq(irq_find_mapping(lnw->domain,
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base + gpio));
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}
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}
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chip->irq_eoi(data);
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}
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static void lnw_irq_init_hw(struct lnw_gpio *lnw)
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{
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void __iomem *reg;
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unsigned base;
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for (base = 0; base < lnw->chip.ngpio; base += 32) {
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/* Clear the rising-edge detect register */
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reg = gpio_reg(&lnw->chip, base, GRER);
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writel(0, reg);
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/* Clear the falling-edge detect register */
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reg = gpio_reg(&lnw->chip, base, GFER);
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writel(0, reg);
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/* Clear the edge detect status register */
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|
reg = gpio_reg(&lnw->chip, base, GEDR);
|
|
writel(~0, reg);
|
|
}
|
|
}
|
|
|
|
static int lnw_gpio_irq_map(struct irq_domain *d, unsigned int virq,
|
|
irq_hw_number_t hw)
|
|
{
|
|
struct lnw_gpio *lnw = d->host_data;
|
|
|
|
irq_set_chip_and_handler_name(virq, &lnw_irqchip, handle_simple_irq,
|
|
"demux");
|
|
irq_set_chip_data(virq, lnw);
|
|
irq_set_irq_type(virq, IRQ_TYPE_NONE);
|
|
|
|
return 0;
|
|
}
|
|
|
|
static const struct irq_domain_ops lnw_gpio_irq_ops = {
|
|
.map = lnw_gpio_irq_map,
|
|
.xlate = irq_domain_xlate_twocell,
|
|
};
|
|
|
|
static int lnw_gpio_runtime_idle(struct device *dev)
|
|
{
|
|
pm_schedule_suspend(dev, 500);
|
|
return -EBUSY;
|
|
}
|
|
|
|
static const struct dev_pm_ops lnw_gpio_pm_ops = {
|
|
SET_RUNTIME_PM_OPS(NULL, NULL, lnw_gpio_runtime_idle)
|
|
};
|
|
|
|
static int lnw_gpio_probe(struct pci_dev *pdev,
|
|
const struct pci_device_id *id)
|
|
{
|
|
void __iomem *base;
|
|
struct lnw_gpio *lnw;
|
|
u32 gpio_base;
|
|
u32 irq_base;
|
|
int retval;
|
|
int ngpio = id->driver_data;
|
|
|
|
retval = pcim_enable_device(pdev);
|
|
if (retval)
|
|
return retval;
|
|
|
|
retval = pcim_iomap_regions(pdev, 1 << 0 | 1 << 1, pci_name(pdev));
|
|
if (retval) {
|
|
dev_err(&pdev->dev, "I/O memory mapping error\n");
|
|
return retval;
|
|
}
|
|
|
|
base = pcim_iomap_table(pdev)[1];
|
|
|
|
irq_base = readl(base);
|
|
gpio_base = readl(sizeof(u32) + base);
|
|
|
|
/* release the IO mapping, since we already get the info from bar1 */
|
|
pcim_iounmap_regions(pdev, 1 << 1);
|
|
|
|
lnw = devm_kzalloc(&pdev->dev, sizeof(*lnw), GFP_KERNEL);
|
|
if (!lnw) {
|
|
dev_err(&pdev->dev, "can't allocate chip data\n");
|
|
return -ENOMEM;
|
|
}
|
|
|
|
lnw->reg_base = pcim_iomap_table(pdev)[0];
|
|
lnw->chip.label = dev_name(&pdev->dev);
|
|
lnw->chip.request = lnw_gpio_request;
|
|
lnw->chip.direction_input = lnw_gpio_direction_input;
|
|
lnw->chip.direction_output = lnw_gpio_direction_output;
|
|
lnw->chip.get = lnw_gpio_get;
|
|
lnw->chip.set = lnw_gpio_set;
|
|
lnw->chip.to_irq = lnw_gpio_to_irq;
|
|
lnw->chip.base = gpio_base;
|
|
lnw->chip.ngpio = ngpio;
|
|
lnw->chip.can_sleep = 0;
|
|
lnw->pdev = pdev;
|
|
|
|
spin_lock_init(&lnw->lock);
|
|
|
|
lnw->domain = irq_domain_add_simple(pdev->dev.of_node, ngpio, irq_base,
|
|
&lnw_gpio_irq_ops, lnw);
|
|
if (!lnw->domain)
|
|
return -ENOMEM;
|
|
|
|
pci_set_drvdata(pdev, lnw);
|
|
retval = gpiochip_add(&lnw->chip);
|
|
if (retval) {
|
|
dev_err(&pdev->dev, "gpiochip_add error %d\n", retval);
|
|
return retval;
|
|
}
|
|
|
|
lnw_irq_init_hw(lnw);
|
|
|
|
irq_set_handler_data(pdev->irq, lnw);
|
|
irq_set_chained_handler(pdev->irq, lnw_irq_handler);
|
|
|
|
pm_runtime_put_noidle(&pdev->dev);
|
|
pm_runtime_allow(&pdev->dev);
|
|
|
|
return 0;
|
|
}
|
|
|
|
static struct pci_driver lnw_gpio_driver = {
|
|
.name = "langwell_gpio",
|
|
.id_table = lnw_gpio_ids,
|
|
.probe = lnw_gpio_probe,
|
|
.driver = {
|
|
.pm = &lnw_gpio_pm_ops,
|
|
},
|
|
};
|
|
|
|
static int __init lnw_gpio_init(void)
|
|
{
|
|
return pci_register_driver(&lnw_gpio_driver);
|
|
}
|
|
|
|
device_initcall(lnw_gpio_init);
|