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The new Armada 375 and Armada 38x Marvell SoCs are based on Cortex-A9 CPU cores and use the ARM GIC as their main interrupt controller. However, for various purposes (wake-up from suspend, MSI interrupts), they have kept a separate MPIC interrupt controller, acting as a slave to the GIC. This MPIC was already used as the primary controller on previous Marvell SoCs, so this commit extends the existing driver to allow the MPIC to be used as a GIC slave. Reviewed-by: Gregory CLEMENT <gregory.clement@free-electrons.com> Signed-off-by: Ezequiel Garcia <ezequiel.garcia@free-electrons.com> Signed-off-by: Jason Cooper <jason@lakedaemon.net>
39 lines
1.5 KiB
Plaintext
39 lines
1.5 KiB
Plaintext
Marvell Armada 370, 375, 38x, XP Interrupt Controller
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-----------------------------------------------------
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Required properties:
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- compatible: Should be "marvell,mpic"
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- interrupt-controller: Identifies the node as an interrupt controller.
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- msi-controller: Identifies the node as an PCI Message Signaled
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Interrupt controller.
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- #interrupt-cells: The number of cells to define the interrupts. Should be 1.
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The cell is the IRQ number
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- reg: Should contain PMIC registers location and length. First pair
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for the main interrupt registers, second pair for the per-CPU
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interrupt registers. For this last pair, to be compliant with SMP
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support, the "virtual" must be use (For the record, these registers
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automatically map to the interrupt controller registers of the
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current CPU)
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Optional properties:
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- interrupts: If defined, then it indicates that this MPIC is
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connected as a slave to another interrupt controller. This is
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typically the case on Armada 375 and Armada 38x, where the MPIC is
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connected as a slave to the Cortex-A9 GIC. The provided interrupt
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indicate to which GIC interrupt the MPIC output is connected.
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Example:
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mpic: interrupt-controller@d0020000 {
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compatible = "marvell,mpic";
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#interrupt-cells = <1>;
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#address-cells = <1>;
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#size-cells = <1>;
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interrupt-controller;
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msi-controller;
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reg = <0xd0020a00 0x1d0>,
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<0xd0021070 0x58>;
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};
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