Jisheng Zhang 2bf847db0c riscv: extable: add type and data fields ... This is a riscv port of commit d6e2cc5647 ("arm64: extable: add `type` and `data` fields"). Signed-off-by: Jisheng Zhang <jszhang@kernel.org> Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>		2022-01-05 17:52:54 -08:00
..
cacheflush.c	riscv: Flush current cpu icache before other cpus	2021-10-04 18:24:15 -07:00
context.c	riscv: mm: don't advertise 1 num_asid for 0 asid bits	2021-10-04 14:16:58 -07:00
extable.c	riscv: extable: add type and data fields	2022-01-05 17:52:54 -08:00
fault.c	riscv: Enable KFENCE for riscv64	2021-06-30 20:55:41 -07:00
hugetlbpage.c	hugetlbfs: remove hugetlb_add_hstate() warning for existing hstate	2020-06-03 20:09:46 -07:00
init.c	riscv: remove .text section size limitation for XIP	2021-10-26 14:31:15 -07:00
kasan_init.c	riscv: Fix asan-stack clang build	2021-10-29 08:54:50 -07:00
Makefile	riscv: Fixup patch_text panic in ftrace	2021-01-14 15:09:04 -08:00
pageattr.c	RISC-V Patches for the 5.11 Merge Window, Part 1	2020-12-18 10:43:07 -08:00
physaddr.c	riscv: Introduce structure that group all variables regarding kernel mapping	2021-07-05 18:04:00 -07:00
ptdump.c	riscv: Fix PTDUMP output now BPF region moved back to module region	2021-07-06 15:21:27 -07:00
tlbflush.c	riscv: add ASID-based tlbflushing methods	2021-06-30 20:55:39 -07:00