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1.) The DMA programs (struct pcl) are PCI-endian = little endian data (except for the 3rd quadlet in a PCL which the controller does not touch). Annotate them as such. Fix all accesses of the PCL to work with big endian CPUs also. Not actually tested, I only have a little endian PC to test with. This includes replacement of a bitfield struct pcl_status by open-coded shift and mask operations. 2.) The two __attribute__ ((packed)) at struct pcl are not really required since it consists of u32/__le32 only, i.e. there will be no padding with or without the attribute. 3.) The received IEEE 1394 data are byteswapped by the controller from IEEE 1394 endian = big endian to PCI endian = little endian because the PCL_BIGENDIAN control bit is set. Therefore annotate the DMA buffer as a __le32 array. Fix the one access of the DMA buffer (the check of the transaction code of link packets) to work with big endian CPUs. Also fix the two accesses of the client bounce buffer (the reading of packet length). 4.) Add a comment to the userspace ABI header that all of the data gets out as little endian data, except for the timestamp which is CPU endian. (We could make it little endian too, but why? Vice versa, an ioctl could be added to dump packet data in big endian byte order...) Signed-off-by: Stefan Richter <stefanr@s5r6.in-berlin.de>
26 lines
590 B
C
26 lines
590 B
C
#ifndef __nosy_user_h
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#define __nosy_user_h
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#include <linux/ioctl.h>
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#include <linux/types.h>
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#define NOSY_IOC_GET_STATS _IOR('&', 0, struct nosy_stats)
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#define NOSY_IOC_START _IO('&', 1)
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#define NOSY_IOC_STOP _IO('&', 2)
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#define NOSY_IOC_FILTER _IOW('&', 2, __u32)
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struct nosy_stats {
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__u32 total_packet_count;
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__u32 lost_packet_count;
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};
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/*
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* Format of packets returned from the kernel driver:
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*
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* quadlet with timestamp (microseconds, CPU endian)
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* quadlet-padded packet data... (little endian)
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* quadlet with ack (little endian)
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*/
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#endif /* __nosy_user_h */
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