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2fd0237538
Enable devices to signal interrupts via PCI memory cycles. rev6: * fix enable/disable typo, Michael Ellerman rev5: * fix up ack, enable, and disable for iop13xx_msi_chip rev4: * move smp compile fix to separate patch * use dynamic_irq_init in create_irq() * hookup mask/unmask routines in iop13xx_msi_chip rev3: * change msi.c to use linux/smp.h instead of asm/smp.h * call dynamic_irq_cleanup at destroy_irq time rev2: * destroy_irq did not take the full 128 bits of msi_irq_in_use into account * added missing '&' for calls to test_and_set_bit and clear_bit [ebiederm@xmission.com: review comments/suggestions] [dan.j.williams@intel.com: cleanups/forward port to 2.6-git] Signed-off-by: Daniel Wolstenholme <daniel.e.wolstenholme@intel.com> Signed-off-by: Dan Williams <dan.j.williams@intel.com> Acked-by: Eric W. Biederman <ebiederm@xmission.com> Signed-off-by: Andrew Morton <akpm@linux-foundation.org> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
197 lines
6.2 KiB
C
197 lines
6.2 KiB
C
#ifndef _IOP13XX_IRQS_H_
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#define _IOP13XX_IRQS_H_
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#ifndef __ASSEMBLER__
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#include <linux/types.h>
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/* INTPND0 CP6 R0 Page 3
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*/
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static inline u32 read_intpnd_0(void)
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{
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u32 val;
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asm volatile("mrc p6, 0, %0, c0, c3, 0":"=r" (val));
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return val;
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}
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/* INTPND1 CP6 R1 Page 3
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*/
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static inline u32 read_intpnd_1(void)
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{
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u32 val;
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asm volatile("mrc p6, 0, %0, c1, c3, 0":"=r" (val));
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return val;
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}
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/* INTPND2 CP6 R2 Page 3
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*/
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static inline u32 read_intpnd_2(void)
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{
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u32 val;
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asm volatile("mrc p6, 0, %0, c2, c3, 0":"=r" (val));
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return val;
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}
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/* INTPND3 CP6 R3 Page 3
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*/
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static inline u32 read_intpnd_3(void)
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{
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u32 val;
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asm volatile("mrc p6, 0, %0, c3, c3, 0":"=r" (val));
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return val;
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}
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#endif
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#define INTBASE 0
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#define INTSIZE_4 1
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/*
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* iop34x chipset interrupts
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*/
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#define IOP13XX_IRQ(x) (IOP13XX_IRQ_OFS + (x))
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/*
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* On IRQ or FIQ register
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*/
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#define IRQ_IOP13XX_ADMA0_EOT (0)
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#define IRQ_IOP13XX_ADMA0_EOC (1)
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#define IRQ_IOP13XX_ADMA1_EOT (2)
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#define IRQ_IOP13XX_ADMA1_EOC (3)
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#define IRQ_IOP13XX_ADMA2_EOT (4)
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#define IRQ_IOP13XX_ADMA2_EOC (5)
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#define IRQ_IOP134_WATCHDOG (6)
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#define IRQ_IOP13XX_RSVD_7 (7)
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#define IRQ_IOP13XX_TIMER0 (8)
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#define IRQ_IOP13XX_TIMER1 (9)
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#define IRQ_IOP13XX_I2C_0 (10)
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#define IRQ_IOP13XX_I2C_1 (11)
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#define IRQ_IOP13XX_MSG (12)
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#define IRQ_IOP13XX_MSGIBQ (13)
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#define IRQ_IOP13XX_ATU_IM (14)
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#define IRQ_IOP13XX_ATU_BIST (15)
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#define IRQ_IOP13XX_PPMU (16)
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#define IRQ_IOP13XX_COREPMU (17)
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#define IRQ_IOP13XX_CORECACHE (18)
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#define IRQ_IOP13XX_RSVD_19 (19)
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#define IRQ_IOP13XX_RSVD_20 (20)
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#define IRQ_IOP13XX_RSVD_21 (21)
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#define IRQ_IOP13XX_RSVD_22 (22)
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#define IRQ_IOP13XX_RSVD_23 (23)
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#define IRQ_IOP13XX_XINT0 (24)
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#define IRQ_IOP13XX_XINT1 (25)
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#define IRQ_IOP13XX_XINT2 (26)
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#define IRQ_IOP13XX_XINT3 (27)
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#define IRQ_IOP13XX_XINT4 (28)
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#define IRQ_IOP13XX_XINT5 (29)
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#define IRQ_IOP13XX_XINT6 (30)
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#define IRQ_IOP13XX_XINT7 (31)
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/* IINTSRC1 bit */
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#define IRQ_IOP13XX_XINT8 (32) /* 0 */
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#define IRQ_IOP13XX_XINT9 (33) /* 1 */
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#define IRQ_IOP13XX_XINT10 (34) /* 2 */
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#define IRQ_IOP13XX_XINT11 (35) /* 3 */
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#define IRQ_IOP13XX_XINT12 (36) /* 4 */
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#define IRQ_IOP13XX_XINT13 (37) /* 5 */
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#define IRQ_IOP13XX_XINT14 (38) /* 6 */
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#define IRQ_IOP13XX_XINT15 (39) /* 7 */
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#define IRQ_IOP13XX_RSVD_40 (40) /* 8 */
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#define IRQ_IOP13XX_RSVD_41 (41) /* 9 */
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#define IRQ_IOP13XX_RSVD_42 (42) /* 10 */
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#define IRQ_IOP13XX_RSVD_43 (43) /* 11 */
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#define IRQ_IOP13XX_RSVD_44 (44) /* 12 */
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#define IRQ_IOP13XX_RSVD_45 (45) /* 13 */
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#define IRQ_IOP13XX_RSVD_46 (46) /* 14 */
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#define IRQ_IOP13XX_RSVD_47 (47) /* 15 */
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#define IRQ_IOP13XX_RSVD_48 (48) /* 16 */
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#define IRQ_IOP13XX_RSVD_49 (49) /* 17 */
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#define IRQ_IOP13XX_RSVD_50 (50) /* 18 */
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#define IRQ_IOP13XX_UART0 (51) /* 19 */
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#define IRQ_IOP13XX_UART1 (52) /* 20 */
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#define IRQ_IOP13XX_PBIE (53) /* 21 */
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#define IRQ_IOP13XX_ATU_CRW (54) /* 22 */
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#define IRQ_IOP13XX_ATU_ERR (55) /* 23 */
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#define IRQ_IOP13XX_MCU_ERR (56) /* 24 */
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#define IRQ_IOP13XX_ADMA0_ERR (57) /* 25 */
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#define IRQ_IOP13XX_ADMA1_ERR (58) /* 26 */
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#define IRQ_IOP13XX_ADMA2_ERR (59) /* 27 */
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#define IRQ_IOP13XX_RSVD_60 (60) /* 28 */
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#define IRQ_IOP13XX_RSVD_61 (61) /* 29 */
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#define IRQ_IOP13XX_MSG_ERR (62) /* 30 */
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#define IRQ_IOP13XX_RSVD_63 (63) /* 31 */
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/* IINTSRC2 bit */
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#define IRQ_IOP13XX_INTERPROC (64) /* 0 */
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#define IRQ_IOP13XX_RSVD_65 (65) /* 1 */
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#define IRQ_IOP13XX_RSVD_66 (66) /* 2 */
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#define IRQ_IOP13XX_RSVD_67 (67) /* 3 */
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#define IRQ_IOP13XX_RSVD_68 (68) /* 4 */
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#define IRQ_IOP13XX_RSVD_69 (69) /* 5 */
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#define IRQ_IOP13XX_RSVD_70 (70) /* 6 */
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#define IRQ_IOP13XX_RSVD_71 (71) /* 7 */
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#define IRQ_IOP13XX_RSVD_72 (72) /* 8 */
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#define IRQ_IOP13XX_RSVD_73 (73) /* 9 */
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#define IRQ_IOP13XX_RSVD_74 (74) /* 10 */
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#define IRQ_IOP13XX_RSVD_75 (75) /* 11 */
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#define IRQ_IOP13XX_RSVD_76 (76) /* 12 */
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#define IRQ_IOP13XX_RSVD_77 (77) /* 13 */
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#define IRQ_IOP13XX_RSVD_78 (78) /* 14 */
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#define IRQ_IOP13XX_RSVD_79 (79) /* 15 */
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#define IRQ_IOP13XX_RSVD_80 (80) /* 16 */
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#define IRQ_IOP13XX_RSVD_81 (81) /* 17 */
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#define IRQ_IOP13XX_RSVD_82 (82) /* 18 */
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#define IRQ_IOP13XX_RSVD_83 (83) /* 19 */
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#define IRQ_IOP13XX_RSVD_84 (84) /* 20 */
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#define IRQ_IOP13XX_RSVD_85 (85) /* 21 */
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#define IRQ_IOP13XX_RSVD_86 (86) /* 22 */
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#define IRQ_IOP13XX_RSVD_87 (87) /* 23 */
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#define IRQ_IOP13XX_RSVD_88 (88) /* 24 */
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#define IRQ_IOP13XX_RSVD_89 (89) /* 25 */
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#define IRQ_IOP13XX_RSVD_90 (90) /* 26 */
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#define IRQ_IOP13XX_RSVD_91 (91) /* 27 */
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#define IRQ_IOP13XX_RSVD_92 (92) /* 28 */
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#define IRQ_IOP13XX_RSVD_93 (93) /* 29 */
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#define IRQ_IOP13XX_SIB_ERR (94) /* 30 */
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#define IRQ_IOP13XX_SRAM_ERR (95) /* 31 */
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/* IINTSRC3 bit */
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#define IRQ_IOP13XX_I2C_2 (96) /* 0 */
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#define IRQ_IOP13XX_ATUE_BIST (97) /* 1 */
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#define IRQ_IOP13XX_ATUE_CRW (98) /* 2 */
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#define IRQ_IOP13XX_ATUE_ERR (99) /* 3 */
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#define IRQ_IOP13XX_IMU (100) /* 4 */
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#define IRQ_IOP13XX_RSVD_101 (101) /* 5 */
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#define IRQ_IOP13XX_RSVD_102 (102) /* 6 */
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#define IRQ_IOP13XX_TPMI0_OUT (103) /* 7 */
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#define IRQ_IOP13XX_TPMI1_OUT (104) /* 8 */
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#define IRQ_IOP13XX_TPMI2_OUT (105) /* 9 */
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#define IRQ_IOP13XX_TPMI3_OUT (106) /* 10 */
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#define IRQ_IOP13XX_ATUE_IMA (107) /* 11 */
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#define IRQ_IOP13XX_ATUE_IMB (108) /* 12 */
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#define IRQ_IOP13XX_ATUE_IMC (109) /* 13 */
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#define IRQ_IOP13XX_ATUE_IMD (110) /* 14 */
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#define IRQ_IOP13XX_MU_MSI_TB (111) /* 15 */
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#define IRQ_IOP13XX_RSVD_112 (112) /* 16 */
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#define IRQ_IOP13XX_INBD_MSI (113) /* 17 */
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#define IRQ_IOP13XX_RSVD_114 (114) /* 18 */
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#define IRQ_IOP13XX_RSVD_115 (115) /* 19 */
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#define IRQ_IOP13XX_RSVD_116 (116) /* 20 */
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#define IRQ_IOP13XX_RSVD_117 (117) /* 21 */
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#define IRQ_IOP13XX_RSVD_118 (118) /* 22 */
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#define IRQ_IOP13XX_RSVD_119 (119) /* 23 */
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#define IRQ_IOP13XX_RSVD_120 (120) /* 24 */
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#define IRQ_IOP13XX_RSVD_121 (121) /* 25 */
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#define IRQ_IOP13XX_RSVD_122 (122) /* 26 */
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#define IRQ_IOP13XX_RSVD_123 (123) /* 27 */
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#define IRQ_IOP13XX_RSVD_124 (124) /* 28 */
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#define IRQ_IOP13XX_RSVD_125 (125) /* 29 */
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#define IRQ_IOP13XX_RSVD_126 (126) /* 30 */
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#define IRQ_IOP13XX_HPI (127) /* 31 */
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#ifdef CONFIG_PCI_MSI
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#define IRQ_IOP13XX_MSI_0 (IRQ_IOP13XX_HPI + 1)
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#define NR_IOP13XX_IRQS (IRQ_IOP13XX_MSI_0 + 128)
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#else
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#define NR_IOP13XX_IRQS (IRQ_IOP13XX_HPI + 1)
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#endif
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#define NR_IRQS NR_IOP13XX_IRQS
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#endif /* _IOP13XX_IRQ_H_ */
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