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2a4aca1144
Currently, the various forms of low level TLB invalidations are all implemented in misc_32.S for 32-bit processors, in a fairly scary mess of #ifdef's and with interesting duplication such as a whole bunch of code for FSL _tlbie and _tlbia which are no longer used. This moves things around such that _tlbie is now defined in hash_low_32.S and is only used by the 32-bit hash code, and all nohash CPUs use the various _tlbil_* forms that are now moved to a new file, tlb_nohash_low.S. I moved all the definitions for that stuff out of include/asm/tlbflush.h as they are really internal mm stuff, into mm/mmu_decl.h The code should have no functional changes. I kept some variants inline for trivial forms on things like 40x and 8xx. Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org> Acked-by: Kumar Gala <galak@kernel.crashing.org> Signed-off-by: Paul Mackerras <paulus@samba.org>
166 lines
3.7 KiB
ArmAsm
166 lines
3.7 KiB
ArmAsm
/*
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* This file contains low-level functions for performing various
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* types of TLB invalidations on various processors with no hash
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* table.
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*
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* This file implements the following functions for all no-hash
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* processors. Some aren't implemented for some variants. Some
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* are inline in tlbflush.h
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*
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* - tlbil_va
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* - tlbil_pid
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* - tlbil_all
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* - tlbivax_bcast (not yet)
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*
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* Code mostly moved over from misc_32.S
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*
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* Copyright (C) 1995-1996 Gary Thomas (gdt@linuxppc.org)
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*
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* Partially rewritten by Cort Dougan (cort@cs.nmt.edu)
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* Paul Mackerras, Kumar Gala and Benjamin Herrenschmidt.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License
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* as published by the Free Software Foundation; either version
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* 2 of the License, or (at your option) any later version.
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*
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*/
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#include <asm/reg.h>
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#include <asm/page.h>
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#include <asm/cputable.h>
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#include <asm/mmu.h>
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#include <asm/ppc_asm.h>
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#include <asm/asm-offsets.h>
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#include <asm/processor.h>
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#if defined(CONFIG_40x)
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/*
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* 40x implementation needs only tlbil_va
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*/
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_GLOBAL(_tlbil_va)
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/* We run the search with interrupts disabled because we have to change
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* the PID and I don't want to preempt when that happens.
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*/
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mfmsr r5
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mfspr r6,SPRN_PID
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wrteei 0
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mtspr SPRN_PID,r4
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tlbsx. r3, 0, r3
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mtspr SPRN_PID,r6
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wrtee r5
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bne 1f
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sync
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/* There are only 64 TLB entries, so r3 < 64, which means bit 25 is
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* clear. Since 25 is the V bit in the TLB_TAG, loading this value
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* will invalidate the TLB entry. */
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tlbwe r3, r3, TLB_TAG
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isync
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1: blr
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#elif defined(CONFIG_8xx)
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/*
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* Nothing to do for 8xx, everything is inline
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*/
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#elif defined(CONFIG_44x)
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/*
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* 440 implementation uses tlbsx/we for tlbil_va and a full sweep
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* of the TLB for everything else.
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*/
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_GLOBAL(_tlbil_va)
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mfspr r5,SPRN_MMUCR
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rlwimi r5,r4,0,24,31 /* Set TID */
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/* We have to run the search with interrupts disabled, even critical
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* and debug interrupts (in fact the only critical exceptions we have
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* are debug and machine check). Otherwise an interrupt which causes
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* a TLB miss can clobber the MMUCR between the mtspr and the tlbsx. */
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mfmsr r4
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lis r6,(MSR_EE|MSR_CE|MSR_ME|MSR_DE)@ha
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addi r6,r6,(MSR_EE|MSR_CE|MSR_ME|MSR_DE)@l
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andc r6,r4,r6
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mtmsr r6
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mtspr SPRN_MMUCR,r5
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tlbsx. r3, 0, r3
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mtmsr r4
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bne 1f
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sync
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/* There are only 64 TLB entries, so r3 < 64,
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* which means bit 22, is clear. Since 22 is
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* the V bit in the TLB_PAGEID, loading this
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* value will invalidate the TLB entry.
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*/
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tlbwe r3, r3, PPC44x_TLB_PAGEID
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isync
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1: blr
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_GLOBAL(_tlbil_all)
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_GLOBAL(_tlbil_pid)
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li r3,0
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sync
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/* Load high watermark */
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lis r4,tlb_44x_hwater@ha
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lwz r5,tlb_44x_hwater@l(r4)
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1: tlbwe r3,r3,PPC44x_TLB_PAGEID
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addi r3,r3,1
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cmpw 0,r3,r5
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ble 1b
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isync
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blr
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#elif defined(CONFIG_FSL_BOOKE)
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/*
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* FSL BookE implementations. Currently _pid and _all are the
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* same. This will change when tlbilx is actually supported and
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* performs invalidate-by-PID. This change will be driven by
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* mmu_features conditional
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*/
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/*
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* Flush MMU TLB on the local processor
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*/
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_GLOBAL(_tlbil_pid)
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_GLOBAL(_tlbil_all)
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#define MMUCSR0_TLBFI (MMUCSR0_TLB0FI | MMUCSR0_TLB1FI | \
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MMUCSR0_TLB2FI | MMUCSR0_TLB3FI)
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li r3,(MMUCSR0_TLBFI)@l
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mtspr SPRN_MMUCSR0, r3
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1:
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mfspr r3,SPRN_MMUCSR0
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andi. r3,r3,MMUCSR0_TLBFI@l
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bne 1b
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msync
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isync
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blr
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/*
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* Flush MMU TLB for a particular address, but only on the local processor
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* (no broadcast)
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*/
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_GLOBAL(_tlbil_va)
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mfmsr r10
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wrteei 0
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slwi r4,r4,16
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mtspr SPRN_MAS6,r4 /* assume AS=0 for now */
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tlbsx 0,r3
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mfspr r4,SPRN_MAS1 /* check valid */
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andis. r3,r4,MAS1_VALID@h
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beq 1f
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rlwinm r4,r4,0,1,31
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mtspr SPRN_MAS1,r4
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tlbwe
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msync
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isync
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1: wrtee r10
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blr
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#elif
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#error Unsupported processor type !
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#endif
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