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d1e509660c
Use the new 'cpu_has_xfeatures()' function to query AVX CPU support. This has the following advantages to the driver: - Decouples the driver from FPU internals: it's now only using <asm/fpu/api.h>. - Removes detection complexity from the driver, no more raw XGETBV instruction - Shrinks the code a bit. - Standardizes feature name error message printouts across drivers There are also advantages to the x86 FPU code: once all drivers are decoupled from internals we can move them out of common headers and we'll also be able to remove xcr.h. Cc: Andy Lutomirski <luto@amacapital.net> Cc: Borislav Petkov <bp@alien8.de> Cc: Dave Hansen <dave.hansen@linux.intel.com> Cc: Fenghua Yu <fenghua.yu@intel.com> Cc: H. Peter Anvin <hpa@zytor.com> Cc: Linus Torvalds <torvalds@linux-foundation.org> Cc: Oleg Nesterov <oleg@redhat.com> Cc: Peter Zijlstra <peterz@infradead.org> Cc: Thomas Gleixner <tglx@linutronix.de> Signed-off-by: Ingo Molnar <mingo@kernel.org>
191 lines
4.7 KiB
C
191 lines
4.7 KiB
C
/*
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* Cryptographic API.
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*
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* Glue code for the SHA1 Secure Hash Algorithm assembler implementation using
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* Supplemental SSE3 instructions.
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*
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* This file is based on sha1_generic.c
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*
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* Copyright (c) Alan Smithee.
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* Copyright (c) Andrew McDonald <andrew@mcdonald.org.uk>
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* Copyright (c) Jean-Francois Dive <jef@linuxbe.org>
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* Copyright (c) Mathias Krause <minipli@googlemail.com>
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* Copyright (c) Chandramouli Narayanan <mouli@linux.intel.com>
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of the GNU General Public License as published by the Free
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* Software Foundation; either version 2 of the License, or (at your option)
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* any later version.
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*
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*/
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#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
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#include <crypto/internal/hash.h>
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#include <linux/init.h>
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#include <linux/module.h>
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#include <linux/mm.h>
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#include <linux/cryptohash.h>
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#include <linux/types.h>
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#include <crypto/sha.h>
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#include <crypto/sha1_base.h>
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#include <asm/fpu/api.h>
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asmlinkage void sha1_transform_ssse3(u32 *digest, const char *data,
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unsigned int rounds);
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#ifdef CONFIG_AS_AVX
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asmlinkage void sha1_transform_avx(u32 *digest, const char *data,
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unsigned int rounds);
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#endif
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#ifdef CONFIG_AS_AVX2
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#define SHA1_AVX2_BLOCK_OPTSIZE 4 /* optimal 4*64 bytes of SHA1 blocks */
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asmlinkage void sha1_transform_avx2(u32 *digest, const char *data,
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unsigned int rounds);
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#endif
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static void (*sha1_transform_asm)(u32 *, const char *, unsigned int);
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static int sha1_ssse3_update(struct shash_desc *desc, const u8 *data,
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unsigned int len)
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{
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struct sha1_state *sctx = shash_desc_ctx(desc);
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if (!irq_fpu_usable() ||
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(sctx->count % SHA1_BLOCK_SIZE) + len < SHA1_BLOCK_SIZE)
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return crypto_sha1_update(desc, data, len);
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/* make sure casting to sha1_block_fn() is safe */
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BUILD_BUG_ON(offsetof(struct sha1_state, state) != 0);
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kernel_fpu_begin();
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sha1_base_do_update(desc, data, len,
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(sha1_block_fn *)sha1_transform_asm);
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kernel_fpu_end();
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return 0;
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}
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static int sha1_ssse3_finup(struct shash_desc *desc, const u8 *data,
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unsigned int len, u8 *out)
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{
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if (!irq_fpu_usable())
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return crypto_sha1_finup(desc, data, len, out);
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kernel_fpu_begin();
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if (len)
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sha1_base_do_update(desc, data, len,
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(sha1_block_fn *)sha1_transform_asm);
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sha1_base_do_finalize(desc, (sha1_block_fn *)sha1_transform_asm);
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kernel_fpu_end();
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return sha1_base_finish(desc, out);
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}
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/* Add padding and return the message digest. */
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static int sha1_ssse3_final(struct shash_desc *desc, u8 *out)
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{
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return sha1_ssse3_finup(desc, NULL, 0, out);
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}
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#ifdef CONFIG_AS_AVX2
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static void sha1_apply_transform_avx2(u32 *digest, const char *data,
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unsigned int rounds)
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{
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/* Select the optimal transform based on data block size */
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if (rounds >= SHA1_AVX2_BLOCK_OPTSIZE)
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sha1_transform_avx2(digest, data, rounds);
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else
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sha1_transform_avx(digest, data, rounds);
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}
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#endif
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static struct shash_alg alg = {
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.digestsize = SHA1_DIGEST_SIZE,
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.init = sha1_base_init,
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.update = sha1_ssse3_update,
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.final = sha1_ssse3_final,
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.finup = sha1_ssse3_finup,
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.descsize = sizeof(struct sha1_state),
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.base = {
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.cra_name = "sha1",
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.cra_driver_name= "sha1-ssse3",
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.cra_priority = 150,
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.cra_flags = CRYPTO_ALG_TYPE_SHASH,
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.cra_blocksize = SHA1_BLOCK_SIZE,
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.cra_module = THIS_MODULE,
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}
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};
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#ifdef CONFIG_AS_AVX
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static bool __init avx_usable(void)
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{
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if (!cpu_has_xfeatures(XSTATE_SSE | XSTATE_YMM, NULL)) {
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if (cpu_has_avx)
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pr_info("AVX detected but unusable.\n");
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return false;
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}
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return true;
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}
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#ifdef CONFIG_AS_AVX2
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static bool __init avx2_usable(void)
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{
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if (avx_usable() && cpu_has_avx2 && boot_cpu_has(X86_FEATURE_BMI1) &&
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boot_cpu_has(X86_FEATURE_BMI2))
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return true;
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return false;
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}
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#endif
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#endif
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static int __init sha1_ssse3_mod_init(void)
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{
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char *algo_name;
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/* test for SSSE3 first */
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if (cpu_has_ssse3) {
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sha1_transform_asm = sha1_transform_ssse3;
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algo_name = "SSSE3";
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}
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#ifdef CONFIG_AS_AVX
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/* allow AVX to override SSSE3, it's a little faster */
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if (avx_usable()) {
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sha1_transform_asm = sha1_transform_avx;
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algo_name = "AVX";
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#ifdef CONFIG_AS_AVX2
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/* allow AVX2 to override AVX, it's a little faster */
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if (avx2_usable()) {
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sha1_transform_asm = sha1_apply_transform_avx2;
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algo_name = "AVX2";
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}
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#endif
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}
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#endif
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if (sha1_transform_asm) {
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pr_info("Using %s optimized SHA-1 implementation\n", algo_name);
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return crypto_register_shash(&alg);
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}
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pr_info("Neither AVX nor AVX2 nor SSSE3 is available/usable.\n");
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return -ENODEV;
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}
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static void __exit sha1_ssse3_mod_fini(void)
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{
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crypto_unregister_shash(&alg);
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}
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module_init(sha1_ssse3_mod_init);
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module_exit(sha1_ssse3_mod_fini);
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MODULE_LICENSE("GPL");
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MODULE_DESCRIPTION("SHA1 Secure Hash Algorithm, Supplemental SSE3 accelerated");
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MODULE_ALIAS_CRYPTO("sha1");
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