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On some MAX 10 cards, the BMC firmware is not available to service handshake registers during secure update erase and write phases at normal speeds. This problem affects at least hwmon driver. When the MAX 10 hwmon driver tries to read the sensor values during a secure update, the reads are slowed down (e.g., reading all D5005 sensors takes ~24s which is magnitudes worse than the normal <0.02s). Manage access to the handshake registers using a rw semaphore and a FW state variable to prevent accesses during those secure update phases and return -EBUSY instead. If handshake_sys_reg_nranges == 0, don't update bwcfw_state as it is not used. This avoids the locking cost. Co-developed-by: Russ Weight <russell.h.weight@intel.com> Signed-off-by: Russ Weight <russell.h.weight@intel.com> Co-developed-by: Xu Yilun <yilun.xu@intel.com> Signed-off-by: Xu Yilun <yilun.xu@intel.com> Signed-off-by: Ilpo Järvinen <ilpo.jarvinen@linux.intel.com> Signed-off-by: Lee Jones <lee@kernel.org> Link: https://lore.kernel.org/r/20230417092653.16487-5-ilpo.jarvinen@linux.intel.com
184 lines
5.5 KiB
C
184 lines
5.5 KiB
C
// SPDX-License-Identifier: GPL-2.0
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/*
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* Intel MAX 10 Board Management Controller chip
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*
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* Copyright (C) 2018-2020 Intel Corporation. All rights reserved.
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*/
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#include <linux/bitfield.h>
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#include <linux/dev_printk.h>
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#include <linux/init.h>
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#include <linux/mfd/core.h>
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#include <linux/mfd/intel-m10-bmc.h>
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#include <linux/module.h>
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#include <linux/regmap.h>
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#include <linux/spi/spi.h>
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static const struct regmap_range m10bmc_regmap_range[] = {
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regmap_reg_range(M10BMC_N3000_LEGACY_BUILD_VER, M10BMC_N3000_LEGACY_BUILD_VER),
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regmap_reg_range(M10BMC_N3000_SYS_BASE, M10BMC_N3000_SYS_END),
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regmap_reg_range(M10BMC_N3000_FLASH_BASE, M10BMC_N3000_FLASH_END),
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};
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static const struct regmap_access_table m10bmc_access_table = {
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.yes_ranges = m10bmc_regmap_range,
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.n_yes_ranges = ARRAY_SIZE(m10bmc_regmap_range),
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};
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static struct regmap_config intel_m10bmc_regmap_config = {
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.reg_bits = 32,
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.val_bits = 32,
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.reg_stride = 4,
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.wr_table = &m10bmc_access_table,
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.rd_table = &m10bmc_access_table,
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.max_register = M10BMC_N3000_MEM_END,
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};
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static int check_m10bmc_version(struct intel_m10bmc *ddata)
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{
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unsigned int v;
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int ret;
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/*
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* This check is to filter out the very old legacy BMC versions. In the
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* old BMC chips, the BMC version info is stored in the old version
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* register (M10BMC_N3000_LEGACY_BUILD_VER), so its read out value would have
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* not been M10BMC_N3000_VER_LEGACY_INVALID (0xffffffff). But in new BMC
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* chips that the driver supports, the value of this register should be
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* M10BMC_N3000_VER_LEGACY_INVALID.
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*/
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ret = m10bmc_raw_read(ddata, M10BMC_N3000_LEGACY_BUILD_VER, &v);
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if (ret)
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return -ENODEV;
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if (v != M10BMC_N3000_VER_LEGACY_INVALID) {
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dev_err(ddata->dev, "bad version M10BMC detected\n");
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return -ENODEV;
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}
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return 0;
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}
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static int intel_m10_bmc_spi_probe(struct spi_device *spi)
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{
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const struct spi_device_id *id = spi_get_device_id(spi);
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const struct intel_m10bmc_platform_info *info;
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struct device *dev = &spi->dev;
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struct intel_m10bmc *ddata;
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int ret;
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ddata = devm_kzalloc(dev, sizeof(*ddata), GFP_KERNEL);
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if (!ddata)
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return -ENOMEM;
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info = (struct intel_m10bmc_platform_info *)id->driver_data;
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ddata->dev = dev;
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ddata->regmap = devm_regmap_init_spi_avmm(spi, &intel_m10bmc_regmap_config);
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if (IS_ERR(ddata->regmap)) {
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ret = PTR_ERR(ddata->regmap);
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dev_err(dev, "Failed to allocate regmap: %d\n", ret);
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return ret;
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}
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spi_set_drvdata(spi, ddata);
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ret = check_m10bmc_version(ddata);
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if (ret) {
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dev_err(dev, "Failed to identify m10bmc hardware\n");
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return ret;
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}
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return m10bmc_dev_init(ddata, info);
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}
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static const struct m10bmc_csr_map m10bmc_n3000_csr_map = {
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.base = M10BMC_N3000_SYS_BASE,
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.build_version = M10BMC_N3000_BUILD_VER,
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.fw_version = NIOS2_N3000_FW_VERSION,
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.mac_low = M10BMC_N3000_MAC_LOW,
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.mac_high = M10BMC_N3000_MAC_HIGH,
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.doorbell = M10BMC_N3000_DOORBELL,
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.auth_result = M10BMC_N3000_AUTH_RESULT,
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.bmc_prog_addr = M10BMC_N3000_BMC_PROG_ADDR,
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.bmc_reh_addr = M10BMC_N3000_BMC_REH_ADDR,
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.bmc_magic = M10BMC_N3000_BMC_PROG_MAGIC,
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.sr_prog_addr = M10BMC_N3000_SR_PROG_ADDR,
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.sr_reh_addr = M10BMC_N3000_SR_REH_ADDR,
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.sr_magic = M10BMC_N3000_SR_PROG_MAGIC,
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.pr_prog_addr = M10BMC_N3000_PR_PROG_ADDR,
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.pr_reh_addr = M10BMC_N3000_PR_REH_ADDR,
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.pr_magic = M10BMC_N3000_PR_PROG_MAGIC,
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.rsu_update_counter = M10BMC_N3000_STAGING_FLASH_COUNT,
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};
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static struct mfd_cell m10bmc_d5005_subdevs[] = {
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{ .name = "d5005bmc-hwmon" },
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{ .name = "d5005bmc-sec-update" },
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};
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static const struct regmap_range m10bmc_d5005_fw_handshake_regs[] = {
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regmap_reg_range(M10BMC_N3000_TELEM_START, M10BMC_D5005_TELEM_END),
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};
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static struct mfd_cell m10bmc_pacn3000_subdevs[] = {
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{ .name = "n3000bmc-hwmon" },
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{ .name = "n3000bmc-retimer" },
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{ .name = "n3000bmc-sec-update" },
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};
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static const struct regmap_range m10bmc_n3000_fw_handshake_regs[] = {
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regmap_reg_range(M10BMC_N3000_TELEM_START, M10BMC_N3000_TELEM_END),
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};
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static struct mfd_cell m10bmc_n5010_subdevs[] = {
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{ .name = "n5010bmc-hwmon" },
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};
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static const struct intel_m10bmc_platform_info m10bmc_spi_n3000 = {
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.cells = m10bmc_pacn3000_subdevs,
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.n_cells = ARRAY_SIZE(m10bmc_pacn3000_subdevs),
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.handshake_sys_reg_ranges = m10bmc_n3000_fw_handshake_regs,
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.handshake_sys_reg_nranges = ARRAY_SIZE(m10bmc_n3000_fw_handshake_regs),
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.csr_map = &m10bmc_n3000_csr_map,
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};
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static const struct intel_m10bmc_platform_info m10bmc_spi_d5005 = {
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.cells = m10bmc_d5005_subdevs,
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.n_cells = ARRAY_SIZE(m10bmc_d5005_subdevs),
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.handshake_sys_reg_ranges = m10bmc_d5005_fw_handshake_regs,
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.handshake_sys_reg_nranges = ARRAY_SIZE(m10bmc_d5005_fw_handshake_regs),
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.csr_map = &m10bmc_n3000_csr_map,
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};
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static const struct intel_m10bmc_platform_info m10bmc_spi_n5010 = {
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.cells = m10bmc_n5010_subdevs,
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.n_cells = ARRAY_SIZE(m10bmc_n5010_subdevs),
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.handshake_sys_reg_ranges = m10bmc_n3000_fw_handshake_regs,
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.handshake_sys_reg_nranges = ARRAY_SIZE(m10bmc_n3000_fw_handshake_regs),
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.csr_map = &m10bmc_n3000_csr_map,
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};
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static const struct spi_device_id m10bmc_spi_id[] = {
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{ "m10-n3000", (kernel_ulong_t)&m10bmc_spi_n3000 },
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{ "m10-d5005", (kernel_ulong_t)&m10bmc_spi_d5005 },
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{ "m10-n5010", (kernel_ulong_t)&m10bmc_spi_n5010 },
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{ }
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};
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MODULE_DEVICE_TABLE(spi, m10bmc_spi_id);
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static struct spi_driver intel_m10bmc_spi_driver = {
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.driver = {
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.name = "intel-m10-bmc",
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.dev_groups = m10bmc_dev_groups,
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},
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.probe = intel_m10_bmc_spi_probe,
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.id_table = m10bmc_spi_id,
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};
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module_spi_driver(intel_m10bmc_spi_driver);
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MODULE_DESCRIPTION("Intel MAX 10 BMC SPI bus interface");
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MODULE_AUTHOR("Intel Corporation");
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MODULE_LICENSE("GPL v2");
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MODULE_ALIAS("spi:intel-m10-bmc");
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MODULE_IMPORT_NS(INTEL_M10_BMC_CORE);
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