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c5789f419d
If the mdp_* nodes are under an mdp sub-node, their corresponding platform device does not automatically get its iommu assigned properly. Fix this by moving the mdp component nodes up a level such that they are siblings of mdp and all other SoC subsystems. This also simplifies the device tree. Although it fixes iommu assignment issue, it also break compatibility with old device tree. So, the patch in driver is needed to iterate over sibling mdp device nodes, not child ones, to keep driver work properly. Signed-off-by: Minghsiu Tsai <minghsiu.tsai@mediatek.com> Acked-by: Rob Herring <robh@kernel.org> Signed-off-by: Hans Verkuil <hans.verkuil@cisco.com> Signed-off-by: Mauro Carvalho Chehab <mchehab@s-opensource.com>
104 lines
3.4 KiB
Plaintext
104 lines
3.4 KiB
Plaintext
* Mediatek Media Data Path
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Media Data Path is used for scaling and color space conversion.
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Required properties (controller node):
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- compatible: "mediatek,mt8173-mdp"
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- mediatek,vpu: the node of video processor unit, see
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Documentation/devicetree/bindings/media/mediatek-vpu.txt for details.
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Required properties (all function blocks, child node):
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- compatible: Should be one of
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"mediatek,mt8173-mdp-rdma" - read DMA
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"mediatek,mt8173-mdp-rsz" - resizer
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"mediatek,mt8173-mdp-wdma" - write DMA
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"mediatek,mt8173-mdp-wrot" - write DMA with rotation
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- reg: Physical base address and length of the function block register space
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- clocks: device clocks, see
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Documentation/devicetree/bindings/clock/clock-bindings.txt for details.
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- power-domains: a phandle to the power domain, see
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Documentation/devicetree/bindings/power/power_domain.txt for details.
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Required properties (DMA function blocks, child node):
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- compatible: Should be one of
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"mediatek,mt8173-mdp-rdma"
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"mediatek,mt8173-mdp-wdma"
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"mediatek,mt8173-mdp-wrot"
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- iommus: should point to the respective IOMMU block with master port as
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argument, see Documentation/devicetree/bindings/iommu/mediatek,iommu.txt
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for details.
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- mediatek,larb: must contain the local arbiters in the current Socs, see
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Documentation/devicetree/bindings/memory-controllers/mediatek,smi-larb.txt
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for details.
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Example:
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mdp_rdma0: rdma@14001000 {
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compatible = "mediatek,mt8173-mdp-rdma";
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"mediatek,mt8173-mdp";
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reg = <0 0x14001000 0 0x1000>;
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clocks = <&mmsys CLK_MM_MDP_RDMA0>,
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<&mmsys CLK_MM_MUTEX_32K>;
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power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
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iommus = <&iommu M4U_PORT_MDP_RDMA0>;
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mediatek,larb = <&larb0>;
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mediatek,vpu = <&vpu>;
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};
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mdp_rdma1: rdma@14002000 {
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compatible = "mediatek,mt8173-mdp-rdma";
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reg = <0 0x14002000 0 0x1000>;
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clocks = <&mmsys CLK_MM_MDP_RDMA1>,
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<&mmsys CLK_MM_MUTEX_32K>;
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power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
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iommus = <&iommu M4U_PORT_MDP_RDMA1>;
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mediatek,larb = <&larb4>;
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};
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mdp_rsz0: rsz@14003000 {
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compatible = "mediatek,mt8173-mdp-rsz";
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reg = <0 0x14003000 0 0x1000>;
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clocks = <&mmsys CLK_MM_MDP_RSZ0>;
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power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
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};
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mdp_rsz1: rsz@14004000 {
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compatible = "mediatek,mt8173-mdp-rsz";
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reg = <0 0x14004000 0 0x1000>;
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clocks = <&mmsys CLK_MM_MDP_RSZ1>;
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power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
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};
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mdp_rsz2: rsz@14005000 {
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compatible = "mediatek,mt8173-mdp-rsz";
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reg = <0 0x14005000 0 0x1000>;
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clocks = <&mmsys CLK_MM_MDP_RSZ2>;
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power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
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};
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mdp_wdma0: wdma@14006000 {
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compatible = "mediatek,mt8173-mdp-wdma";
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reg = <0 0x14006000 0 0x1000>;
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clocks = <&mmsys CLK_MM_MDP_WDMA>;
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power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
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iommus = <&iommu M4U_PORT_MDP_WDMA>;
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mediatek,larb = <&larb0>;
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};
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mdp_wrot0: wrot@14007000 {
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compatible = "mediatek,mt8173-mdp-wrot";
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reg = <0 0x14007000 0 0x1000>;
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clocks = <&mmsys CLK_MM_MDP_WROT0>;
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power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
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iommus = <&iommu M4U_PORT_MDP_WROT0>;
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mediatek,larb = <&larb0>;
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};
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mdp_wrot1: wrot@14008000 {
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compatible = "mediatek,mt8173-mdp-wrot";
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reg = <0 0x14008000 0 0x1000>;
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clocks = <&mmsys CLK_MM_MDP_WROT1>;
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power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
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iommus = <&iommu M4U_PORT_MDP_WROT1>;
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mediatek,larb = <&larb4>;
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};
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