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edd100634a
ppc_parse_cpu() has been removed since
commit 5b102782c7 ("powerpc/xmon: Enable disassembly
files (compilation changes)"), so remove it.
Signed-off-by: Gaosheng Cui <cuigaosheng1@huawei.com>
Signed-off-by: Michael Ellerman <mpe@ellerman.id.au>
Link: https://lore.kernel.org/r/20220913075029.682327-2-cuigaosheng1@huawei.com
451 lines
16 KiB
C
451 lines
16 KiB
C
/* ppc.h -- Header file for PowerPC opcode table
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Copyright (C) 1994-2016 Free Software Foundation, Inc.
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Written by Ian Lance Taylor, Cygnus Support
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This file is part of GDB, GAS, and the GNU binutils.
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GDB, GAS, and the GNU binutils are free software; you can redistribute
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them and/or modify them under the terms of the GNU General Public
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License as published by the Free Software Foundation; either version
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1, or (at your option) any later version.
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GDB, GAS, and the GNU binutils are distributed in the hope that they
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will be useful, but WITHOUT ANY WARRANTY; without even the implied
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warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See
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the GNU General Public License for more details.
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You should have received a copy of the GNU General Public License
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along with this file; see the file COPYING. If not, write to the Free
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Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA. */
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#ifndef PPC_H
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#define PPC_H
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#ifdef __cplusplus
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extern "C" {
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#endif
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typedef uint64_t ppc_cpu_t;
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/* The opcode table is an array of struct powerpc_opcode. */
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struct powerpc_opcode
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{
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/* The opcode name. */
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const char *name;
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/* The opcode itself. Those bits which will be filled in with
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operands are zeroes. */
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unsigned long opcode;
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/* The opcode mask. This is used by the disassembler. This is a
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mask containing ones indicating those bits which must match the
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opcode field, and zeroes indicating those bits which need not
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match (and are presumably filled in by operands). */
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unsigned long mask;
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/* One bit flags for the opcode. These are used to indicate which
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specific processors support the instructions. The defined values
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are listed below. */
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ppc_cpu_t flags;
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/* One bit flags for the opcode. These are used to indicate which
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specific processors no longer support the instructions. The defined
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values are listed below. */
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ppc_cpu_t deprecated;
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/* An array of operand codes. Each code is an index into the
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operand table. They appear in the order which the operands must
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appear in assembly code, and are terminated by a zero. */
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unsigned char operands[8];
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};
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/* The table itself is sorted by major opcode number, and is otherwise
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in the order in which the disassembler should consider
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instructions. */
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extern const struct powerpc_opcode powerpc_opcodes[];
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extern const int powerpc_num_opcodes;
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extern const struct powerpc_opcode vle_opcodes[];
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extern const int vle_num_opcodes;
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/* Values defined for the flags field of a struct powerpc_opcode. */
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/* Opcode is defined for the PowerPC architecture. */
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#define PPC_OPCODE_PPC 1
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/* Opcode is defined for the POWER (RS/6000) architecture. */
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#define PPC_OPCODE_POWER 2
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/* Opcode is defined for the POWER2 (Rios 2) architecture. */
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#define PPC_OPCODE_POWER2 4
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/* Opcode is supported by the Motorola PowerPC 601 processor. The 601
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is assumed to support all PowerPC (PPC_OPCODE_PPC) instructions,
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but it also supports many additional POWER instructions. */
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#define PPC_OPCODE_601 8
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/* Opcode is supported in both the Power and PowerPC architectures
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(ie, compiler's -mcpu=common or assembler's -mcom). More than just
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the intersection of PPC_OPCODE_PPC with the union of PPC_OPCODE_POWER
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and PPC_OPCODE_POWER2 because many instructions changed mnemonics
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between POWER and POWERPC. */
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#define PPC_OPCODE_COMMON 0x10
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/* Opcode is supported for any Power or PowerPC platform (this is
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for the assembler's -many option, and it eliminates duplicates). */
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#define PPC_OPCODE_ANY 0x20
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/* Opcode is only defined on 64 bit architectures. */
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#define PPC_OPCODE_64 0x40
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/* Opcode is supported as part of the 64-bit bridge. */
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#define PPC_OPCODE_64_BRIDGE 0x80
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/* Opcode is supported by Altivec Vector Unit */
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#define PPC_OPCODE_ALTIVEC 0x100
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/* Opcode is supported by PowerPC 403 processor. */
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#define PPC_OPCODE_403 0x200
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/* Opcode is supported by PowerPC BookE processor. */
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#define PPC_OPCODE_BOOKE 0x400
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/* Opcode is supported by PowerPC 440 processor. */
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#define PPC_OPCODE_440 0x800
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/* Opcode is only supported by Power4 architecture. */
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#define PPC_OPCODE_POWER4 0x1000
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/* Opcode is only supported by Power7 architecture. */
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#define PPC_OPCODE_POWER7 0x2000
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/* Opcode is only supported by e500x2 Core. */
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#define PPC_OPCODE_SPE 0x4000
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/* Opcode is supported by e500x2 Integer select APU. */
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#define PPC_OPCODE_ISEL 0x8000
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/* Opcode is an e500 SPE floating point instruction. */
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#define PPC_OPCODE_EFS 0x10000
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/* Opcode is supported by branch locking APU. */
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#define PPC_OPCODE_BRLOCK 0x20000
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/* Opcode is supported by performance monitor APU. */
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#define PPC_OPCODE_PMR 0x40000
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/* Opcode is supported by cache locking APU. */
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#define PPC_OPCODE_CACHELCK 0x80000
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/* Opcode is supported by machine check APU. */
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#define PPC_OPCODE_RFMCI 0x100000
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/* Opcode is only supported by Power5 architecture. */
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#define PPC_OPCODE_POWER5 0x200000
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/* Opcode is supported by PowerPC e300 family. */
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#define PPC_OPCODE_E300 0x400000
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/* Opcode is only supported by Power6 architecture. */
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#define PPC_OPCODE_POWER6 0x800000
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/* Opcode is only supported by PowerPC Cell family. */
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#define PPC_OPCODE_CELL 0x1000000
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/* Opcode is supported by CPUs with paired singles support. */
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#define PPC_OPCODE_PPCPS 0x2000000
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/* Opcode is supported by Power E500MC */
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#define PPC_OPCODE_E500MC 0x4000000
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/* Opcode is supported by PowerPC 405 processor. */
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#define PPC_OPCODE_405 0x8000000
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/* Opcode is supported by Vector-Scalar (VSX) Unit */
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#define PPC_OPCODE_VSX 0x10000000
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/* Opcode is supported by A2. */
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#define PPC_OPCODE_A2 0x20000000
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/* Opcode is supported by PowerPC 476 processor. */
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#define PPC_OPCODE_476 0x40000000
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/* Opcode is supported by AppliedMicro Titan core */
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#define PPC_OPCODE_TITAN 0x80000000
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/* Opcode which is supported by the e500 family */
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#define PPC_OPCODE_E500 0x100000000ull
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/* Opcode is supported by Extended Altivec Vector Unit */
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#define PPC_OPCODE_ALTIVEC2 0x200000000ull
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/* Opcode is supported by Power E6500 */
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#define PPC_OPCODE_E6500 0x400000000ull
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/* Opcode is supported by Thread management APU */
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#define PPC_OPCODE_TMR 0x800000000ull
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/* Opcode which is supported by the VLE extension. */
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#define PPC_OPCODE_VLE 0x1000000000ull
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/* Opcode is only supported by Power8 architecture. */
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#define PPC_OPCODE_POWER8 0x2000000000ull
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/* Opcode which is supported by the Hardware Transactional Memory extension. */
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/* Currently, this is the same as the POWER8 mask. If another cpu comes out
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that isn't a superset of POWER8, we can define this to its own mask. */
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#define PPC_OPCODE_HTM PPC_OPCODE_POWER8
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/* Opcode is supported by ppc750cl. */
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#define PPC_OPCODE_750 0x4000000000ull
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/* Opcode is supported by ppc7450. */
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#define PPC_OPCODE_7450 0x8000000000ull
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/* Opcode is supported by ppc821/850/860. */
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#define PPC_OPCODE_860 0x10000000000ull
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/* Opcode is only supported by Power9 architecture. */
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#define PPC_OPCODE_POWER9 0x20000000000ull
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/* Opcode is supported by Vector-Scalar (VSX) Unit from ISA 2.08. */
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#define PPC_OPCODE_VSX3 0x40000000000ull
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/* Opcode is supported by e200z4. */
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#define PPC_OPCODE_E200Z4 0x80000000000ull
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/* A macro to extract the major opcode from an instruction. */
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#define PPC_OP(i) (((i) >> 26) & 0x3f)
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/* A macro to determine if the instruction is a 2-byte VLE insn. */
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#define PPC_OP_SE_VLE(m) ((m) <= 0xffff)
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/* A macro to extract the major opcode from a VLE instruction. */
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#define VLE_OP(i,m) (((i) >> ((m) <= 0xffff ? 10 : 26)) & 0x3f)
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/* A macro to convert a VLE opcode to a VLE opcode segment. */
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#define VLE_OP_TO_SEG(i) ((i) >> 1)
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/* The operands table is an array of struct powerpc_operand. */
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struct powerpc_operand
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{
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/* A bitmask of bits in the operand. */
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unsigned int bitm;
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/* The shift operation to be applied to the operand. No shift
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is made if this is zero. For positive values, the operand
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is shifted left by SHIFT. For negative values, the operand
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is shifted right by -SHIFT. Use PPC_OPSHIFT_INV to indicate
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that BITM and SHIFT cannot be used to determine where the
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operand goes in the insn. */
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int shift;
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/* Insertion function. This is used by the assembler. To insert an
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operand value into an instruction, check this field.
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If it is NULL, execute
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if (o->shift >= 0)
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i |= (op & o->bitm) << o->shift;
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else
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i |= (op & o->bitm) >> -o->shift;
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(i is the instruction which we are filling in, o is a pointer to
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this structure, and op is the operand value).
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If this field is not NULL, then simply call it with the
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instruction and the operand value. It will return the new value
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of the instruction. If the ERRMSG argument is not NULL, then if
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the operand value is illegal, *ERRMSG will be set to a warning
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string (the operand will be inserted in any case). If the
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operand value is legal, *ERRMSG will be unchanged (most operands
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can accept any value). */
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unsigned long (*insert)
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(unsigned long instruction, long op, ppc_cpu_t dialect, const char **errmsg);
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/* Extraction function. This is used by the disassembler. To
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extract this operand type from an instruction, check this field.
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If it is NULL, compute
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if (o->shift >= 0)
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op = (i >> o->shift) & o->bitm;
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else
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op = (i << -o->shift) & o->bitm;
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if ((o->flags & PPC_OPERAND_SIGNED) != 0)
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sign_extend (op);
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(i is the instruction, o is a pointer to this structure, and op
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is the result).
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If this field is not NULL, then simply call it with the
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instruction value. It will return the value of the operand. If
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the INVALID argument is not NULL, *INVALID will be set to
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non-zero if this operand type can not actually be extracted from
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this operand (i.e., the instruction does not match). If the
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operand is valid, *INVALID will not be changed. */
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long (*extract) (unsigned long instruction, ppc_cpu_t dialect, int *invalid);
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/* One bit syntax flags. */
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unsigned long flags;
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};
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/* Elements in the table are retrieved by indexing with values from
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the operands field of the powerpc_opcodes table. */
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extern const struct powerpc_operand powerpc_operands[];
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extern const unsigned int num_powerpc_operands;
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/* Use with the shift field of a struct powerpc_operand to indicate
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that BITM and SHIFT cannot be used to determine where the operand
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goes in the insn. */
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#define PPC_OPSHIFT_INV (-1U << 31)
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/* Values defined for the flags field of a struct powerpc_operand. */
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/* This operand takes signed values. */
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#define PPC_OPERAND_SIGNED (0x1)
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/* This operand takes signed values, but also accepts a full positive
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range of values when running in 32 bit mode. That is, if bits is
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16, it takes any value from -0x8000 to 0xffff. In 64 bit mode,
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this flag is ignored. */
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#define PPC_OPERAND_SIGNOPT (0x2)
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/* This operand does not actually exist in the assembler input. This
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is used to support extended mnemonics such as mr, for which two
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operands fields are identical. The assembler should call the
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insert function with any op value. The disassembler should call
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the extract function, ignore the return value, and check the value
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placed in the valid argument. */
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#define PPC_OPERAND_FAKE (0x4)
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/* The next operand should be wrapped in parentheses rather than
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separated from this one by a comma. This is used for the load and
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store instructions which want their operands to look like
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reg,displacement(reg)
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*/
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#define PPC_OPERAND_PARENS (0x8)
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/* This operand may use the symbolic names for the CR fields, which
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are
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lt 0 gt 1 eq 2 so 3 un 3
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cr0 0 cr1 1 cr2 2 cr3 3
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cr4 4 cr5 5 cr6 6 cr7 7
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These may be combined arithmetically, as in cr2*4+gt. These are
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only supported on the PowerPC, not the POWER. */
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#define PPC_OPERAND_CR_BIT (0x10)
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/* This operand names a register. The disassembler uses this to print
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register names with a leading 'r'. */
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#define PPC_OPERAND_GPR (0x20)
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/* Like PPC_OPERAND_GPR, but don't print a leading 'r' for r0. */
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#define PPC_OPERAND_GPR_0 (0x40)
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/* This operand names a floating point register. The disassembler
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prints these with a leading 'f'. */
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#define PPC_OPERAND_FPR (0x80)
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/* This operand is a relative branch displacement. The disassembler
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prints these symbolically if possible. */
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#define PPC_OPERAND_RELATIVE (0x100)
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/* This operand is an absolute branch address. The disassembler
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prints these symbolically if possible. */
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#define PPC_OPERAND_ABSOLUTE (0x200)
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/* This operand is optional, and is zero if omitted. This is used for
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example, in the optional BF field in the comparison instructions. The
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assembler must count the number of operands remaining on the line,
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and the number of operands remaining for the opcode, and decide
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whether this operand is present or not. The disassembler should
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print this operand out only if it is not zero. */
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#define PPC_OPERAND_OPTIONAL (0x400)
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/* This flag is only used with PPC_OPERAND_OPTIONAL. If this operand
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is omitted, then for the next operand use this operand value plus
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1, ignoring the next operand field for the opcode. This wretched
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hack is needed because the Power rotate instructions can take
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either 4 or 5 operands. The disassembler should print this operand
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out regardless of the PPC_OPERAND_OPTIONAL field. */
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#define PPC_OPERAND_NEXT (0x800)
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/* This operand should be regarded as a negative number for the
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purposes of overflow checking (i.e., the normal most negative
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number is disallowed and one more than the normal most positive
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number is allowed). This flag will only be set for a signed
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operand. */
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#define PPC_OPERAND_NEGATIVE (0x1000)
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/* This operand names a vector unit register. The disassembler
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prints these with a leading 'v'. */
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#define PPC_OPERAND_VR (0x2000)
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/* This operand is for the DS field in a DS form instruction. */
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#define PPC_OPERAND_DS (0x4000)
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/* This operand is for the DQ field in a DQ form instruction. */
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#define PPC_OPERAND_DQ (0x8000)
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/* Valid range of operand is 0..n rather than 0..n-1. */
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#define PPC_OPERAND_PLUS1 (0x10000)
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/* Xilinx APU and FSL related operands */
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#define PPC_OPERAND_FSL (0x20000)
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#define PPC_OPERAND_FCR (0x40000)
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#define PPC_OPERAND_UDI (0x80000)
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/* This operand names a vector-scalar unit register. The disassembler
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prints these with a leading 'vs'. */
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#define PPC_OPERAND_VSR (0x100000)
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/* This is a CR FIELD that does not use symbolic names. */
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#define PPC_OPERAND_CR_REG (0x200000)
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/* This flag is only used with PPC_OPERAND_OPTIONAL. If this operand
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is omitted, then the value it should use for the operand is stored
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in the SHIFT field of the immediatly following operand field. */
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#define PPC_OPERAND_OPTIONAL_VALUE (0x400000)
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/* This flag is only used with PPC_OPERAND_OPTIONAL. The operand is
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only optional when generating 32-bit code. */
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#define PPC_OPERAND_OPTIONAL32 (0x800000)
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/* The POWER and PowerPC assemblers use a few macros. We keep them
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with the operands table for simplicity. The macro table is an
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array of struct powerpc_macro. */
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struct powerpc_macro
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{
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/* The macro name. */
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const char *name;
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/* The number of operands the macro takes. */
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unsigned int operands;
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/* One bit flags for the opcode. These are used to indicate which
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specific processors support the instructions. The values are the
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same as those for the struct powerpc_opcode flags field. */
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ppc_cpu_t flags;
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/* A format string to turn the macro into a normal instruction.
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Each %N in the string is replaced with operand number N (zero
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based). */
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const char *format;
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};
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extern const struct powerpc_macro powerpc_macros[];
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extern const int powerpc_num_macros;
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static inline long
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ppc_optional_operand_value (const struct powerpc_operand *operand)
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{
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if ((operand->flags & PPC_OPERAND_OPTIONAL_VALUE) != 0)
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return (operand+1)->shift;
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return 0;
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}
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#ifdef __cplusplus
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}
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#endif
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#endif /* PPC_H */
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