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Introduce PLL clock controller for Amlogic A1 SoC family. The clock unit is an APB slave module that is designed for generating all of the internal and system clocks. The SoC uses an external 24MHz crystal; there are 4 internal PLLs: SYS_PLL/HIFI_PLL/USB_PLL/(FIXPLL), these PLLs generate 27 clock sources. Signed-off-by: Jian Hu <jian.hu@amlogic.com> Signed-off-by: Dmitry Rokosov <ddrokosov@sberdevices.ru> Reviewed-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com> Link: https://lore.kernel.org/r/20230523135351.19133-5-ddrokosov@sberdevices.ru Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
23 lines
952 B
Makefile
23 lines
952 B
Makefile
# SPDX-License-Identifier: GPL-2.0-only
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# Amlogic clock drivers
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obj-$(CONFIG_COMMON_CLK_MESON_AO_CLKC) += meson-aoclk.o
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obj-$(CONFIG_COMMON_CLK_MESON_CPU_DYNDIV) += clk-cpu-dyndiv.o
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obj-$(CONFIG_COMMON_CLK_MESON_DUALDIV) += clk-dualdiv.o
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obj-$(CONFIG_COMMON_CLK_MESON_EE_CLKC) += meson-eeclk.o
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obj-$(CONFIG_COMMON_CLK_MESON_MPLL) += clk-mpll.o
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obj-$(CONFIG_COMMON_CLK_MESON_PHASE) += clk-phase.o
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obj-$(CONFIG_COMMON_CLK_MESON_PLL) += clk-pll.o
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obj-$(CONFIG_COMMON_CLK_MESON_REGMAP) += clk-regmap.o
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obj-$(CONFIG_COMMON_CLK_MESON_SCLK_DIV) += sclk-div.o
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obj-$(CONFIG_COMMON_CLK_MESON_VID_PLL_DIV) += vid-pll-div.o
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# Amlogic Clock controllers
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obj-$(CONFIG_COMMON_CLK_AXG) += axg.o axg-aoclk.o
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obj-$(CONFIG_COMMON_CLK_AXG_AUDIO) += axg-audio.o
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obj-$(CONFIG_COMMON_CLK_A1_PLL) += a1-pll.o
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obj-$(CONFIG_COMMON_CLK_GXBB) += gxbb.o gxbb-aoclk.o
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obj-$(CONFIG_COMMON_CLK_G12A) += g12a.o g12a-aoclk.o
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obj-$(CONFIG_COMMON_CLK_MESON8B) += meson8b.o meson8-ddr.o
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