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953e37397f
In order to handle emulation of prefixed instructions in the guest, this first makes vcpu->arch.last_inst be an unsigned long, i.e. 64 bits on 64-bit platforms. For prefixed instructions, the upper 32 bits are used for the prefix and the lower 32 bits for the suffix, and both halves are byte-swapped if the guest endianness differs from the host. Next, vcpu->arch.emul_inst is now 64 bits wide, to match the HEIR register on POWER10. Like HEIR, for a prefixed instruction it is defined to have the prefix is in the top 32 bits and the suffix in the bottom 32 bits, with both halves in the correct byte order. kvmppc_get_last_inst is extended on 64-bit machines to put the prefix and suffix in the right places in the ppc_inst_t being returned. kvmppc_load_last_inst now returns the instruction in an unsigned long in the same format as vcpu->arch.last_inst. It makes the decision about whether to fetch a suffix based on the SRR1_PREFIXED bit in the MSR image stored in the vcpu struct, which generally comes from SRR1 or HSRR1 on an interrupt. This bit is defined in Power ISA v3.1B to be set if the interrupt occurred due to a prefixed instruction and cleared otherwise for all interrupts except for instruction storage interrupt, which does not come to the hypervisor. It is set to zero for asynchronous interrupts such as external interrupts. In previous ISA versions it was always set to 0 for all interrupts except instruction storage interrupt. The code in book3s_hv_rmhandlers.S that loads the faulting instruction on a HDSI is only used on POWER8 and therefore doesn't ever need to load a suffix. [npiggin@gmail.com - check that the is-prefixed bit in SRR1 matches the type of instruction that was fetched.] Reviewed-by: Nicholas Piggin <npiggin@gmail.com> Tested-by: Nicholas Piggin <npiggin@gmail.com> Signed-off-by: Paul Mackerras <paulus@ozlabs.org> Signed-off-by: Michael Ellerman <mpe@ellerman.id.au> Link: https://msgid.link/ZAgsq9h1CCzouQuV@cleo
314 lines
6.9 KiB
C
314 lines
6.9 KiB
C
// SPDX-License-Identifier: GPL-2.0-only
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/*
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*
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* Copyright IBM Corp. 2007
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* Copyright 2011 Freescale Semiconductor, Inc.
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*
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* Authors: Hollis Blanchard <hollisb@us.ibm.com>
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*/
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#include <linux/jiffies.h>
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#include <linux/hrtimer.h>
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#include <linux/types.h>
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#include <linux/string.h>
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#include <linux/kvm_host.h>
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#include <linux/clockchips.h>
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#include <asm/reg.h>
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#include <asm/time.h>
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#include <asm/byteorder.h>
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#include <asm/kvm_ppc.h>
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#include <asm/disassemble.h>
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#include <asm/ppc-opcode.h>
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#include "timing.h"
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#include "trace.h"
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void kvmppc_emulate_dec(struct kvm_vcpu *vcpu)
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{
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unsigned long dec_nsec;
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unsigned long long dec_time;
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pr_debug("mtDEC: %lx\n", vcpu->arch.dec);
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hrtimer_try_to_cancel(&vcpu->arch.dec_timer);
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#ifdef CONFIG_PPC_BOOK3S
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/* mtdec lowers the interrupt line when positive. */
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kvmppc_core_dequeue_dec(vcpu);
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#endif
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#ifdef CONFIG_BOOKE
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/* On BOOKE, DEC = 0 is as good as decrementer not enabled */
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if (vcpu->arch.dec == 0)
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return;
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#endif
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/*
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* The decrementer ticks at the same rate as the timebase, so
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* that's how we convert the guest DEC value to the number of
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* host ticks.
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*/
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dec_time = vcpu->arch.dec;
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/*
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* Guest timebase ticks at the same frequency as host timebase.
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* So use the host timebase calculations for decrementer emulation.
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*/
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dec_time = tb_to_ns(dec_time);
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dec_nsec = do_div(dec_time, NSEC_PER_SEC);
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hrtimer_start(&vcpu->arch.dec_timer,
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ktime_set(dec_time, dec_nsec), HRTIMER_MODE_REL);
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vcpu->arch.dec_jiffies = get_tb();
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}
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u32 kvmppc_get_dec(struct kvm_vcpu *vcpu, u64 tb)
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{
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u64 jd = tb - vcpu->arch.dec_jiffies;
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#ifdef CONFIG_BOOKE
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if (vcpu->arch.dec < jd)
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return 0;
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#endif
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return vcpu->arch.dec - jd;
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}
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static int kvmppc_emulate_mtspr(struct kvm_vcpu *vcpu, int sprn, int rs)
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{
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enum emulation_result emulated = EMULATE_DONE;
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ulong spr_val = kvmppc_get_gpr(vcpu, rs);
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switch (sprn) {
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case SPRN_SRR0:
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kvmppc_set_srr0(vcpu, spr_val);
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break;
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case SPRN_SRR1:
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kvmppc_set_srr1(vcpu, spr_val);
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break;
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/* XXX We need to context-switch the timebase for
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* watchdog and FIT. */
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case SPRN_TBWL: break;
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case SPRN_TBWU: break;
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case SPRN_DEC:
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vcpu->arch.dec = (u32) spr_val;
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kvmppc_emulate_dec(vcpu);
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break;
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case SPRN_SPRG0:
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kvmppc_set_sprg0(vcpu, spr_val);
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break;
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case SPRN_SPRG1:
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kvmppc_set_sprg1(vcpu, spr_val);
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break;
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case SPRN_SPRG2:
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kvmppc_set_sprg2(vcpu, spr_val);
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break;
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case SPRN_SPRG3:
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kvmppc_set_sprg3(vcpu, spr_val);
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break;
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/* PIR can legally be written, but we ignore it */
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case SPRN_PIR: break;
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default:
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emulated = vcpu->kvm->arch.kvm_ops->emulate_mtspr(vcpu, sprn,
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spr_val);
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if (emulated == EMULATE_FAIL)
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printk(KERN_INFO "mtspr: unknown spr "
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"0x%x\n", sprn);
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break;
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}
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kvmppc_set_exit_type(vcpu, EMULATED_MTSPR_EXITS);
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return emulated;
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}
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static int kvmppc_emulate_mfspr(struct kvm_vcpu *vcpu, int sprn, int rt)
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{
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enum emulation_result emulated = EMULATE_DONE;
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ulong spr_val = 0;
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switch (sprn) {
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case SPRN_SRR0:
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spr_val = kvmppc_get_srr0(vcpu);
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break;
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case SPRN_SRR1:
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spr_val = kvmppc_get_srr1(vcpu);
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break;
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case SPRN_PVR:
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spr_val = vcpu->arch.pvr;
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break;
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case SPRN_PIR:
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spr_val = vcpu->vcpu_id;
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break;
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/* Note: mftb and TBRL/TBWL are user-accessible, so
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* the guest can always access the real TB anyways.
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* In fact, we probably will never see these traps. */
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case SPRN_TBWL:
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spr_val = get_tb() >> 32;
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break;
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case SPRN_TBWU:
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spr_val = get_tb();
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break;
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case SPRN_SPRG0:
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spr_val = kvmppc_get_sprg0(vcpu);
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break;
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case SPRN_SPRG1:
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spr_val = kvmppc_get_sprg1(vcpu);
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break;
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case SPRN_SPRG2:
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spr_val = kvmppc_get_sprg2(vcpu);
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break;
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case SPRN_SPRG3:
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spr_val = kvmppc_get_sprg3(vcpu);
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break;
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/* Note: SPRG4-7 are user-readable, so we don't get
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* a trap. */
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case SPRN_DEC:
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spr_val = kvmppc_get_dec(vcpu, get_tb());
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break;
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default:
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emulated = vcpu->kvm->arch.kvm_ops->emulate_mfspr(vcpu, sprn,
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&spr_val);
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if (unlikely(emulated == EMULATE_FAIL)) {
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printk(KERN_INFO "mfspr: unknown spr "
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"0x%x\n", sprn);
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}
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break;
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}
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if (emulated == EMULATE_DONE)
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kvmppc_set_gpr(vcpu, rt, spr_val);
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kvmppc_set_exit_type(vcpu, EMULATED_MFSPR_EXITS);
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return emulated;
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}
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/* XXX Should probably auto-generate instruction decoding for a particular core
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* from opcode tables in the future. */
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int kvmppc_emulate_instruction(struct kvm_vcpu *vcpu)
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{
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u32 inst;
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ppc_inst_t pinst;
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int rs, rt, sprn;
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enum emulation_result emulated;
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int advance = 1;
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/* this default type might be overwritten by subcategories */
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kvmppc_set_exit_type(vcpu, EMULATED_INST_EXITS);
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emulated = kvmppc_get_last_inst(vcpu, INST_GENERIC, &pinst);
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inst = ppc_inst_val(pinst);
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if (emulated != EMULATE_DONE)
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return emulated;
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pr_debug("Emulating opcode %d / %d\n", get_op(inst), get_xop(inst));
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rs = get_rs(inst);
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rt = get_rt(inst);
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sprn = get_sprn(inst);
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switch (get_op(inst)) {
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case OP_TRAP:
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#ifdef CONFIG_PPC_BOOK3S
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case OP_TRAP_64:
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kvmppc_core_queue_program(vcpu, SRR1_PROGTRAP);
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#else
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kvmppc_core_queue_program(vcpu,
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vcpu->arch.shared->esr | ESR_PTR);
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#endif
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advance = 0;
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break;
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case 31:
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switch (get_xop(inst)) {
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case OP_31_XOP_TRAP:
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#ifdef CONFIG_64BIT
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case OP_31_XOP_TRAP_64:
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#endif
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#ifdef CONFIG_PPC_BOOK3S
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kvmppc_core_queue_program(vcpu, SRR1_PROGTRAP);
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#else
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kvmppc_core_queue_program(vcpu,
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vcpu->arch.shared->esr | ESR_PTR);
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#endif
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advance = 0;
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break;
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case OP_31_XOP_MFSPR:
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emulated = kvmppc_emulate_mfspr(vcpu, sprn, rt);
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if (emulated == EMULATE_AGAIN) {
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emulated = EMULATE_DONE;
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advance = 0;
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}
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break;
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case OP_31_XOP_MTSPR:
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emulated = kvmppc_emulate_mtspr(vcpu, sprn, rs);
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if (emulated == EMULATE_AGAIN) {
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emulated = EMULATE_DONE;
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advance = 0;
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}
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break;
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case OP_31_XOP_TLBSYNC:
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break;
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default:
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/* Attempt core-specific emulation below. */
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emulated = EMULATE_FAIL;
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}
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break;
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case 0:
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/*
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* Instruction with primary opcode 0. Based on PowerISA
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* these are illegal instructions.
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*/
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if (inst == KVMPPC_INST_SW_BREAKPOINT) {
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vcpu->run->exit_reason = KVM_EXIT_DEBUG;
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vcpu->run->debug.arch.status = 0;
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vcpu->run->debug.arch.address = kvmppc_get_pc(vcpu);
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emulated = EMULATE_EXIT_USER;
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advance = 0;
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} else
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emulated = EMULATE_FAIL;
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break;
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default:
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emulated = EMULATE_FAIL;
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}
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if (emulated == EMULATE_FAIL) {
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emulated = vcpu->kvm->arch.kvm_ops->emulate_op(vcpu, inst,
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&advance);
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if (emulated == EMULATE_AGAIN) {
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advance = 0;
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} else if (emulated == EMULATE_FAIL) {
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advance = 0;
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printk(KERN_ERR "Couldn't emulate instruction 0x%08x "
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"(op %d xop %d)\n", inst, get_op(inst), get_xop(inst));
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}
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}
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trace_kvm_ppc_instr(inst, kvmppc_get_pc(vcpu), emulated);
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/* Advance past emulated instruction. */
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/*
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* If this ever handles prefixed instructions, the 4
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* will need to become ppc_inst_len(pinst) instead.
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*/
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if (advance)
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kvmppc_set_pc(vcpu, kvmppc_get_pc(vcpu) + 4);
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return emulated;
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}
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EXPORT_SYMBOL_GPL(kvmppc_emulate_instruction);
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