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05492f2fd8
The LSE atomics are implemented using alternative code sequences of different lengths, and explicit NOP padding is used to ensure the patching works correctly. This patch converts the bulk of the LSE code over to using the __nops macro, which makes it slightly clearer as to what is going on and also consolidates all of the padding at the end of the various sequences. Signed-off-by: Will Deacon <will.deacon@arm.com>
277 lines
7.8 KiB
C
277 lines
7.8 KiB
C
/*
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* Based on arch/arm/include/asm/cmpxchg.h
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*
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* Copyright (C) 2012 ARM Ltd.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program. If not, see <http://www.gnu.org/licenses/>.
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*/
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#ifndef __ASM_CMPXCHG_H
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#define __ASM_CMPXCHG_H
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#include <linux/bug.h>
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#include <asm/atomic.h>
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#include <asm/barrier.h>
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#include <asm/lse.h>
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/*
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* We need separate acquire parameters for ll/sc and lse, since the full
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* barrier case is generated as release+dmb for the former and
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* acquire+release for the latter.
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*/
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#define __XCHG_CASE(w, sz, name, mb, nop_lse, acq, acq_lse, rel, cl) \
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static inline unsigned long __xchg_case_##name(unsigned long x, \
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volatile void *ptr) \
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{ \
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unsigned long ret, tmp; \
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\
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asm volatile(ARM64_LSE_ATOMIC_INSN( \
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/* LL/SC */ \
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" prfm pstl1strm, %2\n" \
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"1: ld" #acq "xr" #sz "\t%" #w "0, %2\n" \
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" st" #rel "xr" #sz "\t%w1, %" #w "3, %2\n" \
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" cbnz %w1, 1b\n" \
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" " #mb, \
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/* LSE atomics */ \
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" swp" #acq_lse #rel #sz "\t%" #w "3, %" #w "0, %2\n" \
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__nops(3) \
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" " #nop_lse) \
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: "=&r" (ret), "=&r" (tmp), "+Q" (*(u8 *)ptr) \
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: "r" (x) \
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: cl); \
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\
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return ret; \
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}
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__XCHG_CASE(w, b, 1, , , , , , )
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__XCHG_CASE(w, h, 2, , , , , , )
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__XCHG_CASE(w, , 4, , , , , , )
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__XCHG_CASE( , , 8, , , , , , )
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__XCHG_CASE(w, b, acq_1, , , a, a, , "memory")
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__XCHG_CASE(w, h, acq_2, , , a, a, , "memory")
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__XCHG_CASE(w, , acq_4, , , a, a, , "memory")
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__XCHG_CASE( , , acq_8, , , a, a, , "memory")
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__XCHG_CASE(w, b, rel_1, , , , , l, "memory")
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__XCHG_CASE(w, h, rel_2, , , , , l, "memory")
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__XCHG_CASE(w, , rel_4, , , , , l, "memory")
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__XCHG_CASE( , , rel_8, , , , , l, "memory")
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__XCHG_CASE(w, b, mb_1, dmb ish, nop, , a, l, "memory")
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__XCHG_CASE(w, h, mb_2, dmb ish, nop, , a, l, "memory")
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__XCHG_CASE(w, , mb_4, dmb ish, nop, , a, l, "memory")
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__XCHG_CASE( , , mb_8, dmb ish, nop, , a, l, "memory")
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#undef __XCHG_CASE
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#define __XCHG_GEN(sfx) \
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static inline unsigned long __xchg##sfx(unsigned long x, \
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volatile void *ptr, \
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int size) \
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{ \
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switch (size) { \
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case 1: \
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return __xchg_case##sfx##_1(x, ptr); \
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case 2: \
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return __xchg_case##sfx##_2(x, ptr); \
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case 4: \
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return __xchg_case##sfx##_4(x, ptr); \
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case 8: \
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return __xchg_case##sfx##_8(x, ptr); \
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default: \
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BUILD_BUG(); \
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} \
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\
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unreachable(); \
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}
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__XCHG_GEN()
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__XCHG_GEN(_acq)
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__XCHG_GEN(_rel)
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__XCHG_GEN(_mb)
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#undef __XCHG_GEN
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#define __xchg_wrapper(sfx, ptr, x) \
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({ \
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__typeof__(*(ptr)) __ret; \
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__ret = (__typeof__(*(ptr))) \
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__xchg##sfx((unsigned long)(x), (ptr), sizeof(*(ptr))); \
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__ret; \
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})
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/* xchg */
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#define xchg_relaxed(...) __xchg_wrapper( , __VA_ARGS__)
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#define xchg_acquire(...) __xchg_wrapper(_acq, __VA_ARGS__)
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#define xchg_release(...) __xchg_wrapper(_rel, __VA_ARGS__)
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#define xchg(...) __xchg_wrapper( _mb, __VA_ARGS__)
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#define __CMPXCHG_GEN(sfx) \
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static inline unsigned long __cmpxchg##sfx(volatile void *ptr, \
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unsigned long old, \
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unsigned long new, \
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int size) \
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{ \
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switch (size) { \
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case 1: \
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return __cmpxchg_case##sfx##_1(ptr, (u8)old, new); \
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case 2: \
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return __cmpxchg_case##sfx##_2(ptr, (u16)old, new); \
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case 4: \
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return __cmpxchg_case##sfx##_4(ptr, old, new); \
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case 8: \
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return __cmpxchg_case##sfx##_8(ptr, old, new); \
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default: \
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BUILD_BUG(); \
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} \
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\
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unreachable(); \
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}
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__CMPXCHG_GEN()
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__CMPXCHG_GEN(_acq)
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__CMPXCHG_GEN(_rel)
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__CMPXCHG_GEN(_mb)
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#undef __CMPXCHG_GEN
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#define __cmpxchg_wrapper(sfx, ptr, o, n) \
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({ \
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__typeof__(*(ptr)) __ret; \
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__ret = (__typeof__(*(ptr))) \
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__cmpxchg##sfx((ptr), (unsigned long)(o), \
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(unsigned long)(n), sizeof(*(ptr))); \
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__ret; \
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})
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/* cmpxchg */
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#define cmpxchg_relaxed(...) __cmpxchg_wrapper( , __VA_ARGS__)
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#define cmpxchg_acquire(...) __cmpxchg_wrapper(_acq, __VA_ARGS__)
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#define cmpxchg_release(...) __cmpxchg_wrapper(_rel, __VA_ARGS__)
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#define cmpxchg(...) __cmpxchg_wrapper( _mb, __VA_ARGS__)
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#define cmpxchg_local cmpxchg_relaxed
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/* cmpxchg64 */
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#define cmpxchg64_relaxed cmpxchg_relaxed
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#define cmpxchg64_acquire cmpxchg_acquire
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#define cmpxchg64_release cmpxchg_release
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#define cmpxchg64 cmpxchg
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#define cmpxchg64_local cmpxchg_local
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/* cmpxchg_double */
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#define system_has_cmpxchg_double() 1
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#define __cmpxchg_double_check(ptr1, ptr2) \
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({ \
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if (sizeof(*(ptr1)) != 8) \
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BUILD_BUG(); \
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VM_BUG_ON((unsigned long *)(ptr2) - (unsigned long *)(ptr1) != 1); \
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})
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#define cmpxchg_double(ptr1, ptr2, o1, o2, n1, n2) \
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({\
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int __ret;\
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__cmpxchg_double_check(ptr1, ptr2); \
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__ret = !__cmpxchg_double_mb((unsigned long)(o1), (unsigned long)(o2), \
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(unsigned long)(n1), (unsigned long)(n2), \
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ptr1); \
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__ret; \
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})
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#define cmpxchg_double_local(ptr1, ptr2, o1, o2, n1, n2) \
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({\
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int __ret;\
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__cmpxchg_double_check(ptr1, ptr2); \
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__ret = !__cmpxchg_double((unsigned long)(o1), (unsigned long)(o2), \
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(unsigned long)(n1), (unsigned long)(n2), \
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ptr1); \
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__ret; \
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})
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/* this_cpu_cmpxchg */
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#define _protect_cmpxchg_local(pcp, o, n) \
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({ \
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typeof(*raw_cpu_ptr(&(pcp))) __ret; \
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preempt_disable(); \
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__ret = cmpxchg_local(raw_cpu_ptr(&(pcp)), o, n); \
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preempt_enable(); \
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__ret; \
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})
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#define this_cpu_cmpxchg_1(ptr, o, n) _protect_cmpxchg_local(ptr, o, n)
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#define this_cpu_cmpxchg_2(ptr, o, n) _protect_cmpxchg_local(ptr, o, n)
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#define this_cpu_cmpxchg_4(ptr, o, n) _protect_cmpxchg_local(ptr, o, n)
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#define this_cpu_cmpxchg_8(ptr, o, n) _protect_cmpxchg_local(ptr, o, n)
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#define this_cpu_cmpxchg_double_8(ptr1, ptr2, o1, o2, n1, n2) \
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({ \
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int __ret; \
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preempt_disable(); \
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__ret = cmpxchg_double_local( raw_cpu_ptr(&(ptr1)), \
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raw_cpu_ptr(&(ptr2)), \
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o1, o2, n1, n2); \
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preempt_enable(); \
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__ret; \
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})
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#define __CMPWAIT_CASE(w, sz, name) \
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static inline void __cmpwait_case_##name(volatile void *ptr, \
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unsigned long val) \
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{ \
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unsigned long tmp; \
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\
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asm volatile( \
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" ldxr" #sz "\t%" #w "[tmp], %[v]\n" \
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" eor %" #w "[tmp], %" #w "[tmp], %" #w "[val]\n" \
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" cbnz %" #w "[tmp], 1f\n" \
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" wfe\n" \
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"1:" \
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: [tmp] "=&r" (tmp), [v] "+Q" (*(unsigned long *)ptr) \
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: [val] "r" (val)); \
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}
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__CMPWAIT_CASE(w, b, 1);
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__CMPWAIT_CASE(w, h, 2);
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__CMPWAIT_CASE(w, , 4);
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__CMPWAIT_CASE( , , 8);
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#undef __CMPWAIT_CASE
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#define __CMPWAIT_GEN(sfx) \
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static inline void __cmpwait##sfx(volatile void *ptr, \
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unsigned long val, \
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int size) \
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{ \
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switch (size) { \
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case 1: \
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return __cmpwait_case##sfx##_1(ptr, (u8)val); \
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case 2: \
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return __cmpwait_case##sfx##_2(ptr, (u16)val); \
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case 4: \
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return __cmpwait_case##sfx##_4(ptr, val); \
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case 8: \
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return __cmpwait_case##sfx##_8(ptr, val); \
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default: \
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BUILD_BUG(); \
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} \
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\
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unreachable(); \
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}
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__CMPWAIT_GEN()
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#undef __CMPWAIT_GEN
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#define __cmpwait_relaxed(ptr, val) \
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__cmpwait((ptr), (unsigned long)(val), sizeof(*(ptr)))
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#endif /* __ASM_CMPXCHG_H */
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