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The HDMI PHY PLL can be used as an alternative dclk source to RK3588 SoC CRU. It provides more accurate clock rates required by VOP2 to improve existing support for display modes handling, which is known to be problematic when dealing with non-integer refresh rates, among others. It is worth noting this only works for HDMI 2.0 or below, e.g. cannot be used to support HDMI 2.1 4K@120Hz mode. Signed-off-by: Cristian Ciocaltea <cristian.ciocaltea@collabora.com> Link: https://lore.kernel.org/r/20240620-rk3588-hdmiphy-clkprov-v2-4-6a2d2164e508@collabora.com Signed-off-by: Vinod Koul <vkoul@kernel.org> |
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| .. | ||
| Kconfig | ||
| Makefile | ||
| phy-rockchip-dp.c | ||
| phy-rockchip-dphy-rx0.c | ||
| phy-rockchip-emmc.c | ||
| phy-rockchip-inno-csidphy.c | ||
| phy-rockchip-inno-dsidphy.c | ||
| phy-rockchip-inno-hdmi.c | ||
| phy-rockchip-inno-usb2.c | ||
| phy-rockchip-naneng-combphy.c | ||
| phy-rockchip-pcie.c | ||
| phy-rockchip-samsung-hdptx.c | ||
| phy-rockchip-snps-pcie3.c | ||
| phy-rockchip-typec.c | ||
| phy-rockchip-usb.c | ||
| phy-rockchip-usbdp.c | ||