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2795343705
The new clock subsystem was merged in linux-3.4 without any users, this now moves the first three platforms over to it: imx, mxs and spear. The series also contains the changes for the clock subsystem itself, since Mike preferred to have it together with the platforms that require these changes, in order to avoid interdependencies and conflicts. -----BEGIN PGP SIGNATURE----- Version: GnuPG v1.4.11 (GNU/Linux) iQIcBAABAgAGBQJPuexPAAoJEIwa5zzehBx3YBsP/0nFhXjb5t1PdLfFzGKtcZVB j4zXWXMHQ1fA7wIfEpZF3Nnco6MQkufF5wJPoPdn1+wmkzCn3D6IwNVWVtW4U5i9 VGyShSbgusAAYXUe/9yYj8eN+bbRQSvdN4eWYWU6+rRXShGZ5dZZmp+IPNl54dnW 6F8uCnHX0cnIMCpGqV+41zZgZ/4wL2k9gdqu0LO6pi07o4tGd0Z4gcySgUFAnn1R kofNHueYIP4UgOg8DREoBzVKlpRqMou3S2kSZUfMeb3Q9ryF7UIvaGqIILyi7PKL kWd3nptg0EPavfL21SwXHiGpnDpB/Gj/F70kcPLus5RYujB24C9bvBmc26z68NZx Sz9mbElkkIU5duZsl1nxBWJ8IZ/tSWdtmC2xQMznmV7gHyGgVwr4j47f4Uv5sBvM 14JHDO7mqN6E6FnTFZu/oPAN5pDjgL+TVNK5BU6Wkq0zitrA6eyKDqCvBCqkO6Nn tNzOuyRDzMOwM7HzqXhxqtzJWXylO1Mldc4bM8X4Cocf4pnLna/X6uP6dgE6A+JY azVYx4I/0NdEPerDTzIcEhBDgZeBVROhUQr+kHxc4rf6WzUUbu/wEo1UKXWV66oW 1jb1yAFFWqYjkQuQc2PD4JSx35sFJaoSaoneRtmzBzRDfzSr5KjKj1E0e1skyMFq 7ZVLCqZD0cB9DhmMDkWP =rwFF -----END PGP SIGNATURE----- Merge tag 'clock' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc Pull arm-soc clock driver changes from Olof Johansson: "The new clock subsystem was merged in linux-3.4 without any users, this now moves the first three platforms over to it: imx, mxs and spear. The series also contains the changes for the clock subsystem itself, since Mike preferred to have it together with the platforms that require these changes, in order to avoid interdependencies and conflicts." Fix up trivial conflicts in arch/arm/mach-kirkwood/common.c (code removed in one branch, added OF support in another) and drivers/dma/imx-sdma.c (independent changes next to each other). * tag 'clock' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc: (97 commits) clk: Fix CLK_SET_RATE_GATE flag validation in clk_set_rate(). clk: Provide dummy clk_unregister() SPEAr: Update defconfigs SPEAr: Add SMI NOR partition info in dts files SPEAr: Switch to common clock framework SPEAr: Call clk_prepare() before calling clk_enable SPEAr: clk: Add General Purpose Timer Synthesizer clock SPEAr: clk: Add Fractional Synthesizer clock SPEAr: clk: Add Auxiliary Synthesizer clock SPEAr: clk: Add VCO-PLL Synthesizer clock SPEAr: Add DT bindings for SPEAr's timer ARM i.MX: remove now unused clock files ARM: i.MX6: implement clocks using common clock framework ARM i.MX35: implement clocks using common clock framework ARM i.MX5: implement clocks using common clock framework ARM: Kirkwood: Replace clock gating ARM: Orion: Audio: Add clk/clkdev support ARM: Orion: PCIE: Add support for clk ARM: Orion: XOR: Add support for clk ARM: Orion: CESA: Add support for clk ...
319 lines
8.3 KiB
C
319 lines
8.3 KiB
C
/*
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* arch/arm/mach-dove/common.c
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*
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* Core functions for Marvell Dove 88AP510 System On Chip
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*
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* This file is licensed under the terms of the GNU General Public
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* License version 2. This program is licensed "as is" without any
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* warranty of any kind, whether express or implied.
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*/
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#include <linux/kernel.h>
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#include <linux/delay.h>
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#include <linux/init.h>
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#include <linux/platform_device.h>
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#include <linux/pci.h>
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#include <linux/clk-provider.h>
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#include <linux/ata_platform.h>
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#include <linux/gpio.h>
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#include <asm/page.h>
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#include <asm/setup.h>
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#include <asm/timex.h>
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#include <asm/hardware/cache-tauros2.h>
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#include <asm/mach/map.h>
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#include <asm/mach/time.h>
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#include <asm/mach/pci.h>
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#include <mach/dove.h>
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#include <mach/bridge-regs.h>
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#include <asm/mach/arch.h>
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#include <linux/irq.h>
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#include <plat/time.h>
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#include <plat/ehci-orion.h>
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#include <plat/common.h>
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#include <plat/addr-map.h>
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#include "common.h"
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static int get_tclk(void);
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/*****************************************************************************
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* I/O Address Mapping
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****************************************************************************/
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static struct map_desc dove_io_desc[] __initdata = {
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{
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.virtual = DOVE_SB_REGS_VIRT_BASE,
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.pfn = __phys_to_pfn(DOVE_SB_REGS_PHYS_BASE),
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.length = DOVE_SB_REGS_SIZE,
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.type = MT_DEVICE,
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}, {
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.virtual = DOVE_NB_REGS_VIRT_BASE,
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.pfn = __phys_to_pfn(DOVE_NB_REGS_PHYS_BASE),
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.length = DOVE_NB_REGS_SIZE,
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.type = MT_DEVICE,
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}, {
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.virtual = DOVE_PCIE0_IO_VIRT_BASE,
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.pfn = __phys_to_pfn(DOVE_PCIE0_IO_PHYS_BASE),
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.length = DOVE_PCIE0_IO_SIZE,
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.type = MT_DEVICE,
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}, {
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.virtual = DOVE_PCIE1_IO_VIRT_BASE,
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.pfn = __phys_to_pfn(DOVE_PCIE1_IO_PHYS_BASE),
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.length = DOVE_PCIE1_IO_SIZE,
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.type = MT_DEVICE,
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},
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};
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void __init dove_map_io(void)
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{
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iotable_init(dove_io_desc, ARRAY_SIZE(dove_io_desc));
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}
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/*****************************************************************************
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* CLK tree
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****************************************************************************/
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static struct clk *tclk;
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static void __init clk_init(void)
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{
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tclk = clk_register_fixed_rate(NULL, "tclk", NULL, CLK_IS_ROOT,
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get_tclk());
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orion_clkdev_init(tclk);
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}
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/*****************************************************************************
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* EHCI0
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****************************************************************************/
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void __init dove_ehci0_init(void)
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{
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orion_ehci_init(DOVE_USB0_PHYS_BASE, IRQ_DOVE_USB0, EHCI_PHY_NA);
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}
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/*****************************************************************************
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* EHCI1
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****************************************************************************/
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void __init dove_ehci1_init(void)
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{
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orion_ehci_1_init(DOVE_USB1_PHYS_BASE, IRQ_DOVE_USB1);
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}
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/*****************************************************************************
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* GE00
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****************************************************************************/
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void __init dove_ge00_init(struct mv643xx_eth_platform_data *eth_data)
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{
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orion_ge00_init(eth_data,
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DOVE_GE00_PHYS_BASE, IRQ_DOVE_GE00_SUM, 0);
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}
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/*****************************************************************************
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* SoC RTC
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****************************************************************************/
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void __init dove_rtc_init(void)
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{
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orion_rtc_init(DOVE_RTC_PHYS_BASE, IRQ_DOVE_RTC);
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}
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/*****************************************************************************
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* SATA
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****************************************************************************/
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void __init dove_sata_init(struct mv_sata_platform_data *sata_data)
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{
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orion_sata_init(sata_data, DOVE_SATA_PHYS_BASE, IRQ_DOVE_SATA);
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}
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/*****************************************************************************
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* UART0
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****************************************************************************/
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void __init dove_uart0_init(void)
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{
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orion_uart0_init(DOVE_UART0_VIRT_BASE, DOVE_UART0_PHYS_BASE,
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IRQ_DOVE_UART_0, tclk);
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}
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/*****************************************************************************
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* UART1
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****************************************************************************/
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void __init dove_uart1_init(void)
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{
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orion_uart1_init(DOVE_UART1_VIRT_BASE, DOVE_UART1_PHYS_BASE,
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IRQ_DOVE_UART_1, tclk);
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}
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/*****************************************************************************
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* UART2
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****************************************************************************/
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void __init dove_uart2_init(void)
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{
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orion_uart2_init(DOVE_UART2_VIRT_BASE, DOVE_UART2_PHYS_BASE,
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IRQ_DOVE_UART_2, tclk);
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}
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/*****************************************************************************
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* UART3
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****************************************************************************/
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void __init dove_uart3_init(void)
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{
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orion_uart3_init(DOVE_UART3_VIRT_BASE, DOVE_UART3_PHYS_BASE,
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IRQ_DOVE_UART_3, tclk);
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}
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/*****************************************************************************
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* SPI
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****************************************************************************/
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void __init dove_spi0_init(void)
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{
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orion_spi_init(DOVE_SPI0_PHYS_BASE);
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}
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void __init dove_spi1_init(void)
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{
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orion_spi_1_init(DOVE_SPI1_PHYS_BASE);
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}
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/*****************************************************************************
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* I2C
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****************************************************************************/
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void __init dove_i2c_init(void)
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{
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orion_i2c_init(DOVE_I2C_PHYS_BASE, IRQ_DOVE_I2C, 10);
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}
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/*****************************************************************************
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* Time handling
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****************************************************************************/
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void __init dove_init_early(void)
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{
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orion_time_set_base(TIMER_VIRT_BASE);
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}
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static int get_tclk(void)
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{
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/* use DOVE_RESET_SAMPLE_HI/LO to detect tclk */
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return 166666667;
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}
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static void __init dove_timer_init(void)
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{
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orion_time_init(BRIDGE_VIRT_BASE, BRIDGE_INT_TIMER1_CLR,
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IRQ_DOVE_BRIDGE, get_tclk());
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}
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struct sys_timer dove_timer = {
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.init = dove_timer_init,
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};
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/*****************************************************************************
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* XOR 0
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****************************************************************************/
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void __init dove_xor0_init(void)
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{
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orion_xor0_init(DOVE_XOR0_PHYS_BASE, DOVE_XOR0_HIGH_PHYS_BASE,
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IRQ_DOVE_XOR_00, IRQ_DOVE_XOR_01);
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}
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/*****************************************************************************
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* XOR 1
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****************************************************************************/
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void __init dove_xor1_init(void)
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{
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orion_xor1_init(DOVE_XOR1_PHYS_BASE, DOVE_XOR1_HIGH_PHYS_BASE,
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IRQ_DOVE_XOR_10, IRQ_DOVE_XOR_11);
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}
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/*****************************************************************************
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* SDIO
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****************************************************************************/
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static u64 sdio_dmamask = DMA_BIT_MASK(32);
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static struct resource dove_sdio0_resources[] = {
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{
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.start = DOVE_SDIO0_PHYS_BASE,
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.end = DOVE_SDIO0_PHYS_BASE + 0xff,
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.flags = IORESOURCE_MEM,
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}, {
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.start = IRQ_DOVE_SDIO0,
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.end = IRQ_DOVE_SDIO0,
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.flags = IORESOURCE_IRQ,
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},
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};
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static struct platform_device dove_sdio0 = {
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.name = "sdhci-dove",
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.id = 0,
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.dev = {
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.dma_mask = &sdio_dmamask,
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.coherent_dma_mask = DMA_BIT_MASK(32),
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},
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.resource = dove_sdio0_resources,
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.num_resources = ARRAY_SIZE(dove_sdio0_resources),
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};
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void __init dove_sdio0_init(void)
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{
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platform_device_register(&dove_sdio0);
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}
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static struct resource dove_sdio1_resources[] = {
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{
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.start = DOVE_SDIO1_PHYS_BASE,
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.end = DOVE_SDIO1_PHYS_BASE + 0xff,
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.flags = IORESOURCE_MEM,
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}, {
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.start = IRQ_DOVE_SDIO1,
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.end = IRQ_DOVE_SDIO1,
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.flags = IORESOURCE_IRQ,
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},
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};
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static struct platform_device dove_sdio1 = {
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.name = "sdhci-dove",
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.id = 1,
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.dev = {
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.dma_mask = &sdio_dmamask,
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.coherent_dma_mask = DMA_BIT_MASK(32),
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},
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.resource = dove_sdio1_resources,
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.num_resources = ARRAY_SIZE(dove_sdio1_resources),
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};
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void __init dove_sdio1_init(void)
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{
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platform_device_register(&dove_sdio1);
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}
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void __init dove_init(void)
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{
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printk(KERN_INFO "Dove 88AP510 SoC, ");
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printk(KERN_INFO "TCLK = %dMHz\n", (get_tclk() + 499999) / 1000000);
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#ifdef CONFIG_CACHE_TAUROS2
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tauros2_init();
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#endif
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dove_setup_cpu_mbus();
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/* Setup root of clk tree */
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clk_init();
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/* internal devices that every board has */
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dove_rtc_init();
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dove_xor0_init();
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dove_xor1_init();
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}
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void dove_restart(char mode, const char *cmd)
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{
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/*
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* Enable soft reset to assert RSTOUTn.
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*/
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writel(SOFT_RESET_OUT_EN, RSTOUTn_MASK);
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/*
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* Assert soft reset.
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*/
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writel(SOFT_RESET, SYSTEM_SOFT_RESET);
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while (1)
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;
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}
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