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755d57b222
Add generic DT board support for the r8a7740 SoC. SCIF serial ports and timers are kept as regular platform devices. Other on-chip and on-board devices should be configured via the device tree. At this point there is no interrupt controller support in place but such code will be added over time when proper IRQ domain support has been added to INTC. Signed-off-by: Magnus Damm <damm@opensource.se> Signed-off-by: Rafael J. Wysocki <rjw@sisk.pl>
766 lines
17 KiB
C
766 lines
17 KiB
C
/*
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* R8A7740 processor support
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*
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* Copyright (C) 2011 Renesas Solutions Corp.
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* Copyright (C) 2011 Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; version 2 of the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
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*/
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#include <linux/delay.h>
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#include <linux/dma-mapping.h>
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#include <linux/kernel.h>
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#include <linux/init.h>
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#include <linux/io.h>
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#include <linux/platform_device.h>
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#include <linux/of_platform.h>
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#include <linux/serial_sci.h>
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#include <linux/sh_dma.h>
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#include <linux/sh_timer.h>
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#include <linux/dma-mapping.h>
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#include <mach/dma-register.h>
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#include <mach/r8a7740.h>
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#include <mach/pm-rmobile.h>
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#include <mach/common.h>
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#include <mach/irqs.h>
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#include <asm/mach-types.h>
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#include <asm/mach/map.h>
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#include <asm/mach/arch.h>
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#include <asm/mach/time.h>
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static struct map_desc r8a7740_io_desc[] __initdata = {
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/*
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* for CPGA/INTC/PFC
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* 0xe6000000-0xefffffff -> 0xe6000000-0xefffffff
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*/
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{
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.virtual = 0xe6000000,
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.pfn = __phys_to_pfn(0xe6000000),
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.length = 160 << 20,
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.type = MT_DEVICE_NONSHARED
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},
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#ifdef CONFIG_CACHE_L2X0
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/*
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* for l2x0_init()
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* 0xf0100000-0xf0101000 -> 0xf0002000-0xf0003000
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*/
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{
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.virtual = 0xf0002000,
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.pfn = __phys_to_pfn(0xf0100000),
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.length = PAGE_SIZE,
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.type = MT_DEVICE_NONSHARED
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},
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#endif
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};
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void __init r8a7740_map_io(void)
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{
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iotable_init(r8a7740_io_desc, ARRAY_SIZE(r8a7740_io_desc));
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/*
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* DMA memory at 0xff200000 - 0xffdfffff. The default 2MB size isn't
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* enough to allocate the frame buffer memory.
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*/
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init_consistent_dma_size(12 << 20);
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}
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/* SCIFA0 */
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static struct plat_sci_port scif0_platform_data = {
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.mapbase = 0xe6c40000,
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.flags = UPF_BOOT_AUTOCONF,
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.scscr = SCSCR_RE | SCSCR_TE,
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.scbrr_algo_id = SCBRR_ALGO_4,
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.type = PORT_SCIFA,
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.irqs = SCIx_IRQ_MUXED(evt2irq(0x0c00)),
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};
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static struct platform_device scif0_device = {
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.name = "sh-sci",
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.id = 0,
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.dev = {
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.platform_data = &scif0_platform_data,
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},
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};
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/* SCIFA1 */
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static struct plat_sci_port scif1_platform_data = {
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.mapbase = 0xe6c50000,
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.flags = UPF_BOOT_AUTOCONF,
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.scscr = SCSCR_RE | SCSCR_TE,
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.scbrr_algo_id = SCBRR_ALGO_4,
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.type = PORT_SCIFA,
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.irqs = SCIx_IRQ_MUXED(evt2irq(0x0c20)),
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};
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static struct platform_device scif1_device = {
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.name = "sh-sci",
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.id = 1,
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.dev = {
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.platform_data = &scif1_platform_data,
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},
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};
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/* SCIFA2 */
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static struct plat_sci_port scif2_platform_data = {
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.mapbase = 0xe6c60000,
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.flags = UPF_BOOT_AUTOCONF,
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.scscr = SCSCR_RE | SCSCR_TE,
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.scbrr_algo_id = SCBRR_ALGO_4,
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.type = PORT_SCIFA,
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.irqs = SCIx_IRQ_MUXED(evt2irq(0x0c40)),
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};
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static struct platform_device scif2_device = {
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.name = "sh-sci",
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.id = 2,
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.dev = {
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.platform_data = &scif2_platform_data,
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},
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};
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/* SCIFA3 */
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static struct plat_sci_port scif3_platform_data = {
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.mapbase = 0xe6c70000,
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.flags = UPF_BOOT_AUTOCONF,
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.scscr = SCSCR_RE | SCSCR_TE,
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.scbrr_algo_id = SCBRR_ALGO_4,
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.type = PORT_SCIFA,
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.irqs = SCIx_IRQ_MUXED(evt2irq(0x0c60)),
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};
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static struct platform_device scif3_device = {
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.name = "sh-sci",
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.id = 3,
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.dev = {
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.platform_data = &scif3_platform_data,
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},
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};
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/* SCIFA4 */
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static struct plat_sci_port scif4_platform_data = {
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.mapbase = 0xe6c80000,
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.flags = UPF_BOOT_AUTOCONF,
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.scscr = SCSCR_RE | SCSCR_TE,
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.scbrr_algo_id = SCBRR_ALGO_4,
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.type = PORT_SCIFA,
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.irqs = SCIx_IRQ_MUXED(evt2irq(0x0d20)),
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};
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static struct platform_device scif4_device = {
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.name = "sh-sci",
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.id = 4,
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.dev = {
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.platform_data = &scif4_platform_data,
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},
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};
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/* SCIFA5 */
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static struct plat_sci_port scif5_platform_data = {
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.mapbase = 0xe6cb0000,
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.flags = UPF_BOOT_AUTOCONF,
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.scscr = SCSCR_RE | SCSCR_TE,
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.scbrr_algo_id = SCBRR_ALGO_4,
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.type = PORT_SCIFA,
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.irqs = SCIx_IRQ_MUXED(evt2irq(0x0d40)),
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};
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static struct platform_device scif5_device = {
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.name = "sh-sci",
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.id = 5,
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.dev = {
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.platform_data = &scif5_platform_data,
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},
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};
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/* SCIFA6 */
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static struct plat_sci_port scif6_platform_data = {
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.mapbase = 0xe6cc0000,
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.flags = UPF_BOOT_AUTOCONF,
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.scscr = SCSCR_RE | SCSCR_TE,
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.scbrr_algo_id = SCBRR_ALGO_4,
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.type = PORT_SCIFA,
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.irqs = SCIx_IRQ_MUXED(evt2irq(0x04c0)),
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};
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static struct platform_device scif6_device = {
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.name = "sh-sci",
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.id = 6,
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.dev = {
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.platform_data = &scif6_platform_data,
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},
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};
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/* SCIFA7 */
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static struct plat_sci_port scif7_platform_data = {
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.mapbase = 0xe6cd0000,
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.flags = UPF_BOOT_AUTOCONF,
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.scscr = SCSCR_RE | SCSCR_TE,
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.scbrr_algo_id = SCBRR_ALGO_4,
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.type = PORT_SCIFA,
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.irqs = SCIx_IRQ_MUXED(evt2irq(0x04e0)),
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};
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static struct platform_device scif7_device = {
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.name = "sh-sci",
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.id = 7,
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.dev = {
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.platform_data = &scif7_platform_data,
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},
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};
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/* SCIFB */
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static struct plat_sci_port scifb_platform_data = {
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.mapbase = 0xe6c30000,
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.flags = UPF_BOOT_AUTOCONF,
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.scscr = SCSCR_RE | SCSCR_TE,
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.scbrr_algo_id = SCBRR_ALGO_4,
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.type = PORT_SCIFB,
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.irqs = SCIx_IRQ_MUXED(evt2irq(0x0d60)),
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};
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static struct platform_device scifb_device = {
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.name = "sh-sci",
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.id = 8,
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.dev = {
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.platform_data = &scifb_platform_data,
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},
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};
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/* CMT */
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static struct sh_timer_config cmt10_platform_data = {
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.name = "CMT10",
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.channel_offset = 0x10,
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.timer_bit = 0,
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.clockevent_rating = 125,
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.clocksource_rating = 125,
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};
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static struct resource cmt10_resources[] = {
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[0] = {
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.name = "CMT10",
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.start = 0xe6138010,
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.end = 0xe613801b,
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.flags = IORESOURCE_MEM,
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},
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[1] = {
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.start = evt2irq(0x0b00),
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.flags = IORESOURCE_IRQ,
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},
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};
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static struct platform_device cmt10_device = {
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.name = "sh_cmt",
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.id = 10,
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.dev = {
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.platform_data = &cmt10_platform_data,
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},
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.resource = cmt10_resources,
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.num_resources = ARRAY_SIZE(cmt10_resources),
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};
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static struct platform_device *r8a7740_early_devices[] __initdata = {
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&scif0_device,
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&scif1_device,
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&scif2_device,
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&scif3_device,
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&scif4_device,
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&scif5_device,
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&scif6_device,
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&scif7_device,
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&scifb_device,
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&cmt10_device,
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};
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/* DMA */
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static const struct sh_dmae_slave_config r8a7740_dmae_slaves[] = {
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{
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.slave_id = SHDMA_SLAVE_SDHI0_TX,
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.addr = 0xe6850030,
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.chcr = CHCR_TX(XMIT_SZ_16BIT),
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.mid_rid = 0xc1,
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}, {
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.slave_id = SHDMA_SLAVE_SDHI0_RX,
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.addr = 0xe6850030,
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.chcr = CHCR_RX(XMIT_SZ_16BIT),
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.mid_rid = 0xc2,
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}, {
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.slave_id = SHDMA_SLAVE_SDHI1_TX,
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.addr = 0xe6860030,
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.chcr = CHCR_TX(XMIT_SZ_16BIT),
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.mid_rid = 0xc9,
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}, {
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.slave_id = SHDMA_SLAVE_SDHI1_RX,
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.addr = 0xe6860030,
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.chcr = CHCR_RX(XMIT_SZ_16BIT),
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.mid_rid = 0xca,
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}, {
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.slave_id = SHDMA_SLAVE_SDHI2_TX,
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.addr = 0xe6870030,
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.chcr = CHCR_TX(XMIT_SZ_16BIT),
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.mid_rid = 0xcd,
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}, {
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.slave_id = SHDMA_SLAVE_SDHI2_RX,
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.addr = 0xe6870030,
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.chcr = CHCR_RX(XMIT_SZ_16BIT),
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.mid_rid = 0xce,
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}, {
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.slave_id = SHDMA_SLAVE_FSIA_TX,
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.addr = 0xfe1f0024,
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.chcr = CHCR_TX(XMIT_SZ_32BIT),
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.mid_rid = 0xb1,
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}, {
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.slave_id = SHDMA_SLAVE_FSIA_RX,
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.addr = 0xfe1f0020,
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.chcr = CHCR_RX(XMIT_SZ_32BIT),
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.mid_rid = 0xb2,
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}, {
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.slave_id = SHDMA_SLAVE_FSIB_TX,
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.addr = 0xfe1f0064,
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.chcr = CHCR_TX(XMIT_SZ_32BIT),
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.mid_rid = 0xb5,
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},
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};
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#define DMA_CHANNEL(a, b, c) \
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{ \
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.offset = a, \
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.dmars = b, \
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.dmars_bit = c, \
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.chclr_offset = (0x220 - 0x20) + a \
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}
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static const struct sh_dmae_channel r8a7740_dmae_channels[] = {
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DMA_CHANNEL(0x00, 0, 0),
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DMA_CHANNEL(0x10, 0, 8),
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DMA_CHANNEL(0x20, 4, 0),
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DMA_CHANNEL(0x30, 4, 8),
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DMA_CHANNEL(0x50, 8, 0),
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DMA_CHANNEL(0x60, 8, 8),
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};
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static struct sh_dmae_pdata dma_platform_data = {
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.slave = r8a7740_dmae_slaves,
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.slave_num = ARRAY_SIZE(r8a7740_dmae_slaves),
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.channel = r8a7740_dmae_channels,
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.channel_num = ARRAY_SIZE(r8a7740_dmae_channels),
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.ts_low_shift = TS_LOW_SHIFT,
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.ts_low_mask = TS_LOW_BIT << TS_LOW_SHIFT,
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.ts_high_shift = TS_HI_SHIFT,
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.ts_high_mask = TS_HI_BIT << TS_HI_SHIFT,
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.ts_shift = dma_ts_shift,
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.ts_shift_num = ARRAY_SIZE(dma_ts_shift),
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.dmaor_init = DMAOR_DME,
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.chclr_present = 1,
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};
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/* Resource order important! */
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static struct resource r8a7740_dmae0_resources[] = {
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{
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/* Channel registers and DMAOR */
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.start = 0xfe008020,
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.end = 0xfe00828f,
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.flags = IORESOURCE_MEM,
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},
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{
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/* DMARSx */
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.start = 0xfe009000,
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.end = 0xfe00900b,
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.flags = IORESOURCE_MEM,
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},
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{
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.name = "error_irq",
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.start = evt2irq(0x20c0),
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.end = evt2irq(0x20c0),
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.flags = IORESOURCE_IRQ,
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},
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{
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/* IRQ for channels 0-5 */
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.start = evt2irq(0x2000),
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.end = evt2irq(0x20a0),
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.flags = IORESOURCE_IRQ,
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},
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};
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/* Resource order important! */
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static struct resource r8a7740_dmae1_resources[] = {
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{
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/* Channel registers and DMAOR */
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.start = 0xfe018020,
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.end = 0xfe01828f,
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.flags = IORESOURCE_MEM,
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},
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{
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/* DMARSx */
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.start = 0xfe019000,
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.end = 0xfe01900b,
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.flags = IORESOURCE_MEM,
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},
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{
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.name = "error_irq",
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.start = evt2irq(0x21c0),
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.end = evt2irq(0x21c0),
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.flags = IORESOURCE_IRQ,
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},
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{
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/* IRQ for channels 0-5 */
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.start = evt2irq(0x2100),
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.end = evt2irq(0x21a0),
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.flags = IORESOURCE_IRQ,
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},
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};
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/* Resource order important! */
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static struct resource r8a7740_dmae2_resources[] = {
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{
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/* Channel registers and DMAOR */
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.start = 0xfe028020,
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.end = 0xfe02828f,
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.flags = IORESOURCE_MEM,
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},
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{
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/* DMARSx */
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.start = 0xfe029000,
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.end = 0xfe02900b,
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.flags = IORESOURCE_MEM,
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},
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{
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.name = "error_irq",
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.start = evt2irq(0x22c0),
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.end = evt2irq(0x22c0),
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.flags = IORESOURCE_IRQ,
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},
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{
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/* IRQ for channels 0-5 */
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.start = evt2irq(0x2200),
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.end = evt2irq(0x22a0),
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.flags = IORESOURCE_IRQ,
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},
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};
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static struct platform_device dma0_device = {
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.name = "sh-dma-engine",
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.id = 0,
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.resource = r8a7740_dmae0_resources,
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.num_resources = ARRAY_SIZE(r8a7740_dmae0_resources),
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.dev = {
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.platform_data = &dma_platform_data,
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},
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};
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static struct platform_device dma1_device = {
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.name = "sh-dma-engine",
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.id = 1,
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.resource = r8a7740_dmae1_resources,
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.num_resources = ARRAY_SIZE(r8a7740_dmae1_resources),
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.dev = {
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.platform_data = &dma_platform_data,
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},
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};
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static struct platform_device dma2_device = {
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.name = "sh-dma-engine",
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.id = 2,
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.resource = r8a7740_dmae2_resources,
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.num_resources = ARRAY_SIZE(r8a7740_dmae2_resources),
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.dev = {
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.platform_data = &dma_platform_data,
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},
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};
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|
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/* USB-DMAC */
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static const struct sh_dmae_channel r8a7740_usb_dma_channels[] = {
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{
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.offset = 0,
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}, {
|
|
.offset = 0x20,
|
|
},
|
|
};
|
|
|
|
static const struct sh_dmae_slave_config r8a7740_usb_dma_slaves[] = {
|
|
{
|
|
.slave_id = SHDMA_SLAVE_USBHS_TX,
|
|
.chcr = USBTS_INDEX2VAL(USBTS_XMIT_SZ_8BYTE),
|
|
}, {
|
|
.slave_id = SHDMA_SLAVE_USBHS_RX,
|
|
.chcr = USBTS_INDEX2VAL(USBTS_XMIT_SZ_8BYTE),
|
|
},
|
|
};
|
|
|
|
static struct sh_dmae_pdata usb_dma_platform_data = {
|
|
.slave = r8a7740_usb_dma_slaves,
|
|
.slave_num = ARRAY_SIZE(r8a7740_usb_dma_slaves),
|
|
.channel = r8a7740_usb_dma_channels,
|
|
.channel_num = ARRAY_SIZE(r8a7740_usb_dma_channels),
|
|
.ts_low_shift = USBTS_LOW_SHIFT,
|
|
.ts_low_mask = USBTS_LOW_BIT << USBTS_LOW_SHIFT,
|
|
.ts_high_shift = USBTS_HI_SHIFT,
|
|
.ts_high_mask = USBTS_HI_BIT << USBTS_HI_SHIFT,
|
|
.ts_shift = dma_usbts_shift,
|
|
.ts_shift_num = ARRAY_SIZE(dma_usbts_shift),
|
|
.dmaor_init = DMAOR_DME,
|
|
.chcr_offset = 0x14,
|
|
.chcr_ie_bit = 1 << 5,
|
|
.dmaor_is_32bit = 1,
|
|
.needs_tend_set = 1,
|
|
.no_dmars = 1,
|
|
.slave_only = 1,
|
|
};
|
|
|
|
static struct resource r8a7740_usb_dma_resources[] = {
|
|
{
|
|
/* Channel registers and DMAOR */
|
|
.start = 0xe68a0020,
|
|
.end = 0xe68a0064 - 1,
|
|
.flags = IORESOURCE_MEM,
|
|
},
|
|
{
|
|
/* VCR/SWR/DMICR */
|
|
.start = 0xe68a0000,
|
|
.end = 0xe68a0014 - 1,
|
|
.flags = IORESOURCE_MEM,
|
|
},
|
|
{
|
|
/* IRQ for channels */
|
|
.start = evt2irq(0x0a00),
|
|
.end = evt2irq(0x0a00),
|
|
.flags = IORESOURCE_IRQ,
|
|
},
|
|
};
|
|
|
|
static struct platform_device usb_dma_device = {
|
|
.name = "sh-dma-engine",
|
|
.id = 3,
|
|
.resource = r8a7740_usb_dma_resources,
|
|
.num_resources = ARRAY_SIZE(r8a7740_usb_dma_resources),
|
|
.dev = {
|
|
.platform_data = &usb_dma_platform_data,
|
|
},
|
|
};
|
|
|
|
/* I2C */
|
|
static struct resource i2c0_resources[] = {
|
|
[0] = {
|
|
.name = "IIC0",
|
|
.start = 0xfff20000,
|
|
.end = 0xfff20425 - 1,
|
|
.flags = IORESOURCE_MEM,
|
|
},
|
|
[1] = {
|
|
.start = intcs_evt2irq(0xe00),
|
|
.end = intcs_evt2irq(0xe60),
|
|
.flags = IORESOURCE_IRQ,
|
|
},
|
|
};
|
|
|
|
static struct resource i2c1_resources[] = {
|
|
[0] = {
|
|
.name = "IIC1",
|
|
.start = 0xe6c20000,
|
|
.end = 0xe6c20425 - 1,
|
|
.flags = IORESOURCE_MEM,
|
|
},
|
|
[1] = {
|
|
.start = evt2irq(0x780), /* IIC1_ALI1 */
|
|
.end = evt2irq(0x7e0), /* IIC1_DTEI1 */
|
|
.flags = IORESOURCE_IRQ,
|
|
},
|
|
};
|
|
|
|
static struct platform_device i2c0_device = {
|
|
.name = "i2c-sh_mobile",
|
|
.id = 0,
|
|
.resource = i2c0_resources,
|
|
.num_resources = ARRAY_SIZE(i2c0_resources),
|
|
};
|
|
|
|
static struct platform_device i2c1_device = {
|
|
.name = "i2c-sh_mobile",
|
|
.id = 1,
|
|
.resource = i2c1_resources,
|
|
.num_resources = ARRAY_SIZE(i2c1_resources),
|
|
};
|
|
|
|
static struct platform_device *r8a7740_late_devices[] __initdata = {
|
|
&i2c0_device,
|
|
&i2c1_device,
|
|
&dma0_device,
|
|
&dma1_device,
|
|
&dma2_device,
|
|
&usb_dma_device,
|
|
};
|
|
|
|
/*
|
|
* r8a7740 chip has lasting errata on MERAM buffer.
|
|
* this is work-around for it.
|
|
* see
|
|
* "Media RAM (MERAM)" on r8a7740 documentation
|
|
*/
|
|
#define MEBUFCNTR 0xFE950098
|
|
void r8a7740_meram_workaround(void)
|
|
{
|
|
void __iomem *reg;
|
|
|
|
reg = ioremap_nocache(MEBUFCNTR, 4);
|
|
if (reg) {
|
|
iowrite32(0x01600164, reg);
|
|
iounmap(reg);
|
|
}
|
|
}
|
|
|
|
#define ICCR 0x0004
|
|
#define ICSTART 0x0070
|
|
|
|
#define i2c_read(reg, offset) ioread8(reg + offset)
|
|
#define i2c_write(reg, offset, data) iowrite8(data, reg + offset)
|
|
|
|
/*
|
|
* r8a7740 chip has lasting errata on I2C I/O pad reset.
|
|
* this is work-around for it.
|
|
*/
|
|
static void r8a7740_i2c_workaround(struct platform_device *pdev)
|
|
{
|
|
struct resource *res;
|
|
void __iomem *reg;
|
|
|
|
res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
|
|
if (unlikely(!res)) {
|
|
pr_err("r8a7740 i2c workaround fail (cannot find resource)\n");
|
|
return;
|
|
}
|
|
|
|
reg = ioremap(res->start, resource_size(res));
|
|
if (unlikely(!reg)) {
|
|
pr_err("r8a7740 i2c workaround fail (cannot map IO)\n");
|
|
return;
|
|
}
|
|
|
|
i2c_write(reg, ICCR, i2c_read(reg, ICCR) | 0x80);
|
|
i2c_read(reg, ICCR); /* dummy read */
|
|
|
|
i2c_write(reg, ICSTART, i2c_read(reg, ICSTART) | 0x10);
|
|
i2c_read(reg, ICSTART); /* dummy read */
|
|
|
|
udelay(10);
|
|
|
|
i2c_write(reg, ICCR, 0x01);
|
|
i2c_write(reg, ICSTART, 0x00);
|
|
|
|
udelay(10);
|
|
|
|
i2c_write(reg, ICCR, 0x10);
|
|
udelay(10);
|
|
i2c_write(reg, ICCR, 0x00);
|
|
udelay(10);
|
|
i2c_write(reg, ICCR, 0x10);
|
|
udelay(10);
|
|
|
|
iounmap(reg);
|
|
}
|
|
|
|
void __init r8a7740_add_standard_devices(void)
|
|
{
|
|
/* I2C work-around */
|
|
r8a7740_i2c_workaround(&i2c0_device);
|
|
r8a7740_i2c_workaround(&i2c1_device);
|
|
|
|
/* PM domain */
|
|
rmobile_init_pm_domain(&r8a7740_pd_a4s);
|
|
rmobile_init_pm_domain(&r8a7740_pd_a3sp);
|
|
rmobile_init_pm_domain(&r8a7740_pd_a4lc);
|
|
|
|
rmobile_pm_add_subdomain(&r8a7740_pd_a4s, &r8a7740_pd_a3sp);
|
|
|
|
/* add devices */
|
|
platform_add_devices(r8a7740_early_devices,
|
|
ARRAY_SIZE(r8a7740_early_devices));
|
|
platform_add_devices(r8a7740_late_devices,
|
|
ARRAY_SIZE(r8a7740_late_devices));
|
|
|
|
/* add devices to PM domain */
|
|
|
|
rmobile_add_device_to_domain(&r8a7740_pd_a3sp, &scif0_device);
|
|
rmobile_add_device_to_domain(&r8a7740_pd_a3sp, &scif1_device);
|
|
rmobile_add_device_to_domain(&r8a7740_pd_a3sp, &scif2_device);
|
|
rmobile_add_device_to_domain(&r8a7740_pd_a3sp, &scif3_device);
|
|
rmobile_add_device_to_domain(&r8a7740_pd_a3sp, &scif4_device);
|
|
rmobile_add_device_to_domain(&r8a7740_pd_a3sp, &scif5_device);
|
|
rmobile_add_device_to_domain(&r8a7740_pd_a3sp, &scif6_device);
|
|
rmobile_add_device_to_domain(&r8a7740_pd_a3sp, &scif7_device);
|
|
rmobile_add_device_to_domain(&r8a7740_pd_a3sp, &scifb_device);
|
|
rmobile_add_device_to_domain(&r8a7740_pd_a3sp, &i2c1_device);
|
|
}
|
|
|
|
static void __init r8a7740_earlytimer_init(void)
|
|
{
|
|
r8a7740_clock_init(0);
|
|
shmobile_earlytimer_init();
|
|
}
|
|
|
|
void __init r8a7740_add_early_devices(void)
|
|
{
|
|
early_platform_add_devices(r8a7740_early_devices,
|
|
ARRAY_SIZE(r8a7740_early_devices));
|
|
|
|
/* setup early console here as well */
|
|
shmobile_setup_console();
|
|
|
|
/* override timer setup with soc-specific code */
|
|
shmobile_timer.init = r8a7740_earlytimer_init;
|
|
}
|
|
|
|
#ifdef CONFIG_USE_OF
|
|
|
|
void __init r8a7740_add_early_devices_dt(void)
|
|
{
|
|
shmobile_setup_delay(800, 1, 3); /* Cortex-A9 @ 800MHz */
|
|
|
|
early_platform_add_devices(r8a7740_early_devices,
|
|
ARRAY_SIZE(r8a7740_early_devices));
|
|
|
|
/* setup early console here as well */
|
|
shmobile_setup_console();
|
|
}
|
|
|
|
static const struct of_dev_auxdata r8a7740_auxdata_lookup[] __initconst = {
|
|
{ }
|
|
};
|
|
|
|
void __init r8a7740_add_standard_devices_dt(void)
|
|
{
|
|
/* clocks are setup late during boot in the case of DT */
|
|
r8a7740_clock_init(0);
|
|
|
|
platform_add_devices(r8a7740_early_devices,
|
|
ARRAY_SIZE(r8a7740_early_devices));
|
|
|
|
of_platform_populate(NULL, of_default_bus_match_table,
|
|
r8a7740_auxdata_lookup, NULL);
|
|
}
|
|
|
|
static const char *r8a7740_boards_compat_dt[] __initdata = {
|
|
"renesas,r8a7740",
|
|
NULL,
|
|
};
|
|
|
|
DT_MACHINE_START(SH7372_DT, "Generic R8A7740 (Flattened Device Tree)")
|
|
.map_io = r8a7740_map_io,
|
|
.init_early = r8a7740_add_early_devices_dt,
|
|
.init_irq = r8a7740_init_irq,
|
|
.handle_irq = shmobile_handle_irq_intc,
|
|
.init_machine = r8a7740_add_standard_devices_dt,
|
|
.timer = &shmobile_timer,
|
|
.dt_compat = r8a7740_boards_compat_dt,
|
|
MACHINE_END
|
|
|
|
#endif /* CONFIG_USE_OF */
|