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88801d043b
When device on dom0 side has been reset, the vpci on Xen side won't get notification, so that the cached state in vpci is all out of date with the real device state. To solve that problem, add a new function to clear all vpci device state when device is reset on dom0 side. And call that function in pcistub_init_device. Because when using "pci-assignable-add" to assign a passthrough device in Xen, it will reset passthrough device and the vpci state will out of date, and then device will fail to restore bar state. Signed-off-by: Jiqian Chen <Jiqian.Chen@amd.com> Signed-off-by: Huang Rui <ray.huang@amd.com> Signed-off-by: Jiqian Chen <Jiqian.Chen@amd.com> Reviewed-by: Stefano Stabellini <sstabellini@kernel.org> Message-ID: <20240924061437.2636766-2-Jiqian.Chen@amd.com> Signed-off-by: Juergen Gross <jgross@suse.com>
321 lines
7.7 KiB
C
321 lines
7.7 KiB
C
/* SPDX-License-Identifier: MIT */
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#ifndef __XEN_PUBLIC_PHYSDEV_H__
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#define __XEN_PUBLIC_PHYSDEV_H__
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/*
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* Prototype for this hypercall is:
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* int physdev_op(int cmd, void *args)
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* @cmd == PHYSDEVOP_??? (physdev operation).
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* @args == Operation-specific extra arguments (NULL if none).
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*/
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/*
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* Notify end-of-interrupt (EOI) for the specified IRQ.
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* @arg == pointer to physdev_eoi structure.
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*/
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#define PHYSDEVOP_eoi 12
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struct physdev_eoi {
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/* IN */
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uint32_t irq;
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};
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/*
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* Register a shared page for the hypervisor to indicate whether the guest
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* must issue PHYSDEVOP_eoi. The semantics of PHYSDEVOP_eoi change slightly
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* once the guest used this function in that the associated event channel
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* will automatically get unmasked. The page registered is used as a bit
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* array indexed by Xen's PIRQ value.
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*/
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#define PHYSDEVOP_pirq_eoi_gmfn_v1 17
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/*
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* Register a shared page for the hypervisor to indicate whether the
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* guest must issue PHYSDEVOP_eoi. This hypercall is very similar to
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* PHYSDEVOP_pirq_eoi_gmfn_v1 but it doesn't change the semantics of
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* PHYSDEVOP_eoi. The page registered is used as a bit array indexed by
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* Xen's PIRQ value.
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*/
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#define PHYSDEVOP_pirq_eoi_gmfn_v2 28
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struct physdev_pirq_eoi_gmfn {
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/* IN */
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xen_ulong_t gmfn;
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};
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/*
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* Query the status of an IRQ line.
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* @arg == pointer to physdev_irq_status_query structure.
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*/
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#define PHYSDEVOP_irq_status_query 5
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struct physdev_irq_status_query {
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/* IN */
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uint32_t irq;
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/* OUT */
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uint32_t flags; /* XENIRQSTAT_* */
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};
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/* Need to call PHYSDEVOP_eoi when the IRQ has been serviced? */
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#define _XENIRQSTAT_needs_eoi (0)
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#define XENIRQSTAT_needs_eoi (1U<<_XENIRQSTAT_needs_eoi)
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/* IRQ shared by multiple guests? */
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#define _XENIRQSTAT_shared (1)
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#define XENIRQSTAT_shared (1U<<_XENIRQSTAT_shared)
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/*
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* Set the current VCPU's I/O privilege level.
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* @arg == pointer to physdev_set_iopl structure.
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*/
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#define PHYSDEVOP_set_iopl 6
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struct physdev_set_iopl {
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/* IN */
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uint32_t iopl;
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};
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/*
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* Set the current VCPU's I/O-port permissions bitmap.
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* @arg == pointer to physdev_set_iobitmap structure.
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*/
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#define PHYSDEVOP_set_iobitmap 7
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struct physdev_set_iobitmap {
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/* IN */
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uint8_t * bitmap;
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uint32_t nr_ports;
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};
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/*
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* Read or write an IO-APIC register.
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* @arg == pointer to physdev_apic structure.
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*/
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#define PHYSDEVOP_apic_read 8
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#define PHYSDEVOP_apic_write 9
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struct physdev_apic {
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/* IN */
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unsigned long apic_physbase;
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uint32_t reg;
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/* IN or OUT */
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uint32_t value;
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};
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/*
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* Allocate or free a physical upcall vector for the specified IRQ line.
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* @arg == pointer to physdev_irq structure.
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*/
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#define PHYSDEVOP_alloc_irq_vector 10
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#define PHYSDEVOP_free_irq_vector 11
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struct physdev_irq {
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/* IN */
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uint32_t irq;
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/* IN or OUT */
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uint32_t vector;
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};
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#define MAP_PIRQ_TYPE_MSI 0x0
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#define MAP_PIRQ_TYPE_GSI 0x1
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#define MAP_PIRQ_TYPE_UNKNOWN 0x2
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#define MAP_PIRQ_TYPE_MSI_SEG 0x3
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#define MAP_PIRQ_TYPE_MULTI_MSI 0x4
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#define PHYSDEVOP_map_pirq 13
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struct physdev_map_pirq {
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domid_t domid;
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/* IN */
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int type;
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/* IN */
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int index;
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/* IN or OUT */
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int pirq;
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/* IN - high 16 bits hold segment for ..._MSI_SEG and ..._MULTI_MSI */
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int bus;
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/* IN */
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int devfn;
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/* IN
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* - For MSI-X contains entry number.
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* - For MSI with ..._MULTI_MSI contains number of vectors.
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* OUT (..._MULTI_MSI only)
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* - Number of vectors allocated.
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*/
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int entry_nr;
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/* IN */
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uint64_t table_base;
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};
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#define PHYSDEVOP_unmap_pirq 14
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struct physdev_unmap_pirq {
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domid_t domid;
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/* IN */
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int pirq;
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};
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#define PHYSDEVOP_manage_pci_add 15
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#define PHYSDEVOP_manage_pci_remove 16
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struct physdev_manage_pci {
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/* IN */
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uint8_t bus;
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uint8_t devfn;
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};
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#define PHYSDEVOP_restore_msi 19
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struct physdev_restore_msi {
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/* IN */
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uint8_t bus;
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uint8_t devfn;
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};
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#define PHYSDEVOP_manage_pci_add_ext 20
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struct physdev_manage_pci_ext {
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/* IN */
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uint8_t bus;
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uint8_t devfn;
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unsigned is_extfn;
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unsigned is_virtfn;
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struct {
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uint8_t bus;
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uint8_t devfn;
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} physfn;
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};
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/*
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* Argument to physdev_op_compat() hypercall. Superceded by new physdev_op()
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* hypercall since 0x00030202.
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*/
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struct physdev_op {
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uint32_t cmd;
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union {
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struct physdev_irq_status_query irq_status_query;
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struct physdev_set_iopl set_iopl;
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struct physdev_set_iobitmap set_iobitmap;
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struct physdev_apic apic_op;
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struct physdev_irq irq_op;
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} u;
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};
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#define PHYSDEVOP_setup_gsi 21
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struct physdev_setup_gsi {
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int gsi;
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/* IN */
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uint8_t triggering;
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/* IN */
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uint8_t polarity;
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/* IN */
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};
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#define PHYSDEVOP_get_nr_pirqs 22
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struct physdev_nr_pirqs {
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/* OUT */
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uint32_t nr_pirqs;
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};
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/* type is MAP_PIRQ_TYPE_GSI or MAP_PIRQ_TYPE_MSI
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* the hypercall returns a free pirq */
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#define PHYSDEVOP_get_free_pirq 23
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struct physdev_get_free_pirq {
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/* IN */
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int type;
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/* OUT */
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uint32_t pirq;
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};
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#define XEN_PCI_DEV_EXTFN 0x1
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#define XEN_PCI_DEV_VIRTFN 0x2
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#define XEN_PCI_DEV_PXM 0x4
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#define XEN_PCI_MMCFG_RESERVED 0x1
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#define PHYSDEVOP_pci_mmcfg_reserved 24
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struct physdev_pci_mmcfg_reserved {
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uint64_t address;
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uint16_t segment;
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uint8_t start_bus;
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uint8_t end_bus;
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uint32_t flags;
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};
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#define PHYSDEVOP_pci_device_add 25
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struct physdev_pci_device_add {
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/* IN */
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uint16_t seg;
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uint8_t bus;
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uint8_t devfn;
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uint32_t flags;
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struct {
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uint8_t bus;
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uint8_t devfn;
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} physfn;
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#if defined(__STDC_VERSION__) && __STDC_VERSION__ >= 199901L
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uint32_t optarr[];
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#elif defined(__GNUC__)
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uint32_t optarr[0];
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#endif
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};
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#define PHYSDEVOP_pci_device_remove 26
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#define PHYSDEVOP_restore_msi_ext 27
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/*
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* Dom0 should use these two to announce MMIO resources assigned to
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* MSI-X capable devices won't (prepare) or may (release) change.
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*/
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#define PHYSDEVOP_prepare_msix 30
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#define PHYSDEVOP_release_msix 31
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/*
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* Notify the hypervisor that a PCI device has been reset, so that any
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* internally cached state is regenerated. Should be called after any
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* device reset performed by the hardware domain.
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*/
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#define PHYSDEVOP_pci_device_reset 32
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struct physdev_pci_device {
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/* IN */
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uint16_t seg;
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uint8_t bus;
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uint8_t devfn;
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};
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struct pci_device_reset {
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struct physdev_pci_device dev;
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#define PCI_DEVICE_RESET_COLD 0x0
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#define PCI_DEVICE_RESET_WARM 0x1
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#define PCI_DEVICE_RESET_HOT 0x2
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#define PCI_DEVICE_RESET_FLR 0x3
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#define PCI_DEVICE_RESET_MASK 0x3
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uint32_t flags;
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};
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#define PHYSDEVOP_DBGP_RESET_PREPARE 1
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#define PHYSDEVOP_DBGP_RESET_DONE 2
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#define PHYSDEVOP_DBGP_BUS_UNKNOWN 0
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#define PHYSDEVOP_DBGP_BUS_PCI 1
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#define PHYSDEVOP_dbgp_op 29
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struct physdev_dbgp_op {
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/* IN */
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uint8_t op;
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uint8_t bus;
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union {
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struct physdev_pci_device pci;
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} u;
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};
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/*
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* Notify that some PIRQ-bound event channels have been unmasked.
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* ** This command is obsolete since interface version 0x00030202 and is **
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* ** unsupported by newer versions of Xen. **
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*/
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#define PHYSDEVOP_IRQ_UNMASK_NOTIFY 4
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/*
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* These all-capitals physdev operation names are superceded by the new names
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* (defined above) since interface version 0x00030202.
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*/
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#define PHYSDEVOP_IRQ_STATUS_QUERY PHYSDEVOP_irq_status_query
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#define PHYSDEVOP_SET_IOPL PHYSDEVOP_set_iopl
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#define PHYSDEVOP_SET_IOBITMAP PHYSDEVOP_set_iobitmap
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#define PHYSDEVOP_APIC_READ PHYSDEVOP_apic_read
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#define PHYSDEVOP_APIC_WRITE PHYSDEVOP_apic_write
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#define PHYSDEVOP_ASSIGN_VECTOR PHYSDEVOP_alloc_irq_vector
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#define PHYSDEVOP_FREE_VECTOR PHYSDEVOP_free_irq_vector
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#define PHYSDEVOP_IRQ_NEEDS_UNMASK_NOTIFY XENIRQSTAT_needs_eoi
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#define PHYSDEVOP_IRQ_SHARED XENIRQSTAT_shared
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#endif /* __XEN_PUBLIC_PHYSDEV_H__ */
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