Uwe Kleine-König 26bac95aa8 clk: divider: fix selection of divider when rounding to closest ... It's an invalid approach to assume that among two divider values the one nearer the exact divider is the better one. Assume a parent rate of 1000 Hz, a divider with CLK_DIVIDER_POWER_OF_TWO and a target rate of 89 Hz. The exact divider is ~ 11.236 so 8 and 16 are the candidates to choose from yielding rates 125 Hz and 62.5 Hz respectivly. While 8 is nearer to 11.236 than 16 is, the latter is still the better divider as 62.5 is nearer to 89 than 125 is. Fixes: 774b514390 (clk: divider: Add round to closest divider) Signed-off-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de> Acked-by: Sascha Hauer <s.hauer@pengutronix.de> Acked-by: Maxime Coquelin <maxime.coquelin@st.com> Signed-off-by: Michael Turquette <mturquette@linaro.org>		2015-03-09 14:19:54 -07:00
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at91	The clock framework changes for 3.20 contain the usual driver additions,	2015-02-21 12:30:30 -08:00
bcm	clk: Add rate constraints to clocks	2015-02-02 14:23:42 -08:00
berlin	clk: berlin: bg2q: remove non-exist "smemc" gate clock	2015-01-13 10:58:43 -08:00
hisilicon	clk: Add rate constraints to clocks	2015-02-02 14:23:42 -08:00
keystone	clk: keystone: gate: fix clk_init_data initialization	2014-02-10 15:17:43 -05:00
mmp	clk: Add rate constraints to clocks	2015-02-02 14:23:42 -08:00
mvebu	clk: mvebu: add suspend/resume for gatable clocks	2014-11-30 16:40:12 +00:00
mxs	Revert "clk: mxs: Fix invalid 32-bit access to frac registers"	2015-02-18 10:13:26 -08:00
pxa	clk: Replace explicit clk assignment with __clk_hw_set_clk	2015-02-18 09:40:11 -08:00
qcom	clk: qcom: fix platform_no_drv_owner.cocci warnings	2015-02-25 12:14:35 -08:00
rockchip	The clock framework changes for 3.20 contain the usual driver additions,	2015-02-21 12:30:30 -08:00
samsung	The clock framework changes for 3.20 contain the usual driver additions,	2015-02-21 12:30:30 -08:00
shmobile	The clock framework changes for 3.20 contain the usual driver additions,	2015-02-21 12:30:30 -08:00
sirf	clk: sirf: update copyright years to 2014	2014-03-26 21:47:35 -07:00
socfpga	Adds support getting the divider registers for the MAIN PLL that was once	2014-05-12 19:11:13 -07:00
spear	Merge branch 'clk-fixes' into clk-next	2014-07-13 07:56:45 -07:00
st	clk: Replace explicit clk assignment with __clk_hw_set_clk	2015-02-18 09:40:11 -08:00
sunxi	The clock framework changes for 3.20 contain the usual driver additions,	2015-02-21 12:30:30 -08:00
tegra	clk: Replace explicit clk assignment with __clk_hw_set_clk	2015-02-18 09:40:11 -08:00
ti	clk: ti: Fix FAPLL parent enable bit handling	2015-02-25 12:06:29 -08:00
ux500	clk: ux500: Drop use of clk-private.h	2015-01-27 11:56:33 -08:00
versatile	ARM: vexpress: Remove non-DT code	2014-11-28 16:08:16 +01:00
x86	clk: x86: drop owner assignment from platform_drivers	2014-10-20 16:20:23 +02:00
zynq	clk: zynq: Force CPU_2X clock to be ungated	2015-01-27 17:00:24 -08:00
clk-asm9260.c	ARM: clk: add clk-asm9260 driver	2015-01-20 10:10:51 -08:00
clk-axi-clkgen.c	clk: Remove .owner field for driver	2014-09-25 17:43:31 -07:00
clk-axm5516.c	clk: drop owner assignment from platform_drivers	2014-10-20 16:20:22 +02:00
clk-bcm2835.c
clk-cdce706.c	clk: TI CDCE706 clock synthesizer driver	2015-01-17 13:52:40 -08:00
clk-clps711x.c	clk: Add CLPS711X clk driver	2014-07-28 23:30:46 -07:00
clk-composite.c	clk: Replace explicit clk assignment with __clk_hw_set_clk	2015-02-18 09:40:11 -08:00
clk-conf.c	clk: Add missing of_clk_set_defaults export	2014-08-04 09:48:39 -07:00
clk-devres.c
clk-divider.c	clk: divider: fix selection of divider when rounding to closest	2015-03-09 14:19:54 -07:00
clk-efm32gg.c	clk/efm32gg: fix dt init prototype	2014-09-09 13:52:18 -07:00
clk-fixed-factor.c
clk-fixed-rate.c
clk-fractional-divider.c	clk: fractional-divider: cast parent_rate to u64 before multiplying	2014-09-10 09:42:37 -07:00
clk-gate.c	clk-gate: fix bit # check in clk_register_gate()	2015-01-20 10:09:05 -08:00
clk-gpio-gate.c	clk: gpio-gate: Ensure gpiod_ APIs are prototyped	2014-09-30 11:57:54 -07:00
clk-highbank.c
clk-ls1x.c	clk: ls1x: Update relationship among all clocks	2014-11-24 07:45:09 +01:00
clk-max77686.c	clk: Remove .owner field for driver	2014-09-25 17:43:31 -07:00
clk-max77802.c	clk: Remove .owner field for driver	2014-09-25 17:43:31 -07:00
clk-max-gen.c	clk: Add generic driver for Maxim PMIC clocks	2014-09-09 13:55:44 -07:00
clk-max-gen.h	clk: Add generic driver for Maxim PMIC clocks	2014-09-09 13:55:44 -07:00
clk-moxart.c	clk: add MOXA ART SoCs clock driver	2014-03-18 17:13:14 -07:00
clk-mux.c	clk: Add clk_unregister_{divider, gate, mux} to close memory leak	2015-01-17 13:52:41 -08:00
clk-nomadik.c	clk: nomadik: fix multiplatform problem	2014-02-26 11:14:44 -08:00
clk-nspire.c
clk-palmas.c	clk: Remove .owner field for driver	2014-09-25 17:43:31 -07:00
clk-qoriq.c	clk: qoriq: Add support for the platform PLL	2015-02-18 09:56:43 -08:00
clk-rk808.c	clk: RK808: add clkout driver for RK808	2014-10-14 02:18:18 +02:00
clk-s2mps11.c	Please consider pulling the clk framework changes toward 3.19. It is	2014-12-20 16:42:36 -08:00
clk-si570.c	clk: si570: Fix email address specifiction	2014-05-20 16:18:18 +02:00
clk-si5351.c	The second half of the clock framework pull requeust for 3.14 is	2014-01-28 18:44:53 -08:00
clk-si5351.h	clk: si5351: remove variant from platform_data	2014-01-27 11:20:22 -08:00
clk-twl6040.c	clk: Remove .owner field for driver	2014-09-25 17:43:31 -07:00
clk-u300.c	clk: u300: Terminate of match table	2014-05-27 18:29:04 -07:00
clk-vt8500.c
clk-wm831x.c	clk: Remove .owner field for driver	2014-09-25 17:43:31 -07:00
clk-xgene.c
clk.c	The clock framework changes for 3.20 contain the usual driver additions,	2015-02-21 12:30:30 -08:00
clk.h	clkdev: Always allocate a struct clk and call __clk_get() w/ CCF	2015-02-06 17:53:20 -08:00
clkdev.c	clkdev: Always allocate a struct clk and call __clk_get() w/ CCF	2015-02-06 17:53:20 -08:00
Kconfig	The clock framework changes for 3.20 contain the usual driver additions,	2015-02-21 12:30:30 -08:00
Makefile	ARM: clk: add clk-asm9260 driver	2015-01-20 10:10:51 -08:00