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26b7a78c55
This converts the lazy dcache handling to the model described in Documentation/cachetlb.txt and drops the ptep_get_and_clear() hacks used for the aliasing dcaches on SH-4 and SH7705 in 32kB mode. As a bonus, this slightly cuts down on the cache flushing frequency. With that and the PTEA handling out of the way, the update_mmu_cache() implementations can be consolidated, and we no longer have to worry about which configuration the cache is in for the SH7705 case. And finally, explicitly disable the lazy writeback on SMP (SH-4A). Signed-off-by: Paul Mundt <lethal@linux-sh.org> |
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| irq | ||
| sh2 | ||
| sh2a | ||
| sh3 | ||
| sh4 | ||
| sh4a | ||
| adc.c | ||
| clock.c | ||
| init.c | ||
| Makefile | ||
| ubc.S | ||