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908dcecda1
Correct the return type of handle_IRQ_event() (inconsistency noticed during Xen development), and remove redundant declarations. The return type adjustment required breaking out the definition of irqreturn_t into a separate header, in order to satisfy current include order dependencies. Signed-off-by: Jan Beulich <jbeulich@novell.com> Cc: Richard Henderson <rth@twiddle.net> Cc: Ivan Kokshaysky <ink@jurassic.park.msu.ru> Cc: Russell King <rmk@arm.linux.org.uk> Cc: Ian Molton <spyro@f2s.com> Cc: Mikael Starvik <starvik@axis.com> Cc: Yoshinori Sato <ysato@users.sourceforge.jp> Cc: Hirokazu Takata <takata.hirokazu@renesas.com> Cc: Heiko Carstens <heiko.carstens@de.ibm.com> Cc: Martin Schwidefsky <schwidefsky@de.ibm.com> Cc: William Lee Irwin III <wli@holomorphy.com> Cc: "David S. Miller" <davem@davemloft.net> Cc: Miles Bader <uclinux-v850@lsi.nec.co.jp> Cc: Geert Uytterhoeven <geert@linux-m68k.org> Cc: Roman Zippel <zippel@linux-m68k.org> Signed-off-by: Andrew Morton <akpm@osdl.org> Signed-off-by: Linus Torvalds <torvalds@osdl.org>
185 lines
5.9 KiB
C
185 lines
5.9 KiB
C
/* $Id: irq.h,v 1.32 2000/08/26 02:42:28 anton Exp $
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* irq.h: IRQ registers on the Sparc.
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*
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* Copyright (C) 1995 David S. Miller (davem@caip.rutgers.edu)
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*/
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#ifndef _SPARC_IRQ_H
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#define _SPARC_IRQ_H
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#include <linux/linkage.h>
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#include <linux/threads.h> /* For NR_CPUS */
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#include <linux/interrupt.h>
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#include <asm/system.h> /* For SUN4M_NCPUS */
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#include <asm/btfixup.h>
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#define __irq_ino(irq) irq
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#define __irq_pil(irq) irq
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#define NR_IRQS 16
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#define irq_canonicalize(irq) (irq)
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/* Dave Redman (djhr@tadpole.co.uk)
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* changed these to function pointers.. it saves cycles and will allow
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* the irq dependencies to be split into different files at a later date
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* sun4c_irq.c, sun4m_irq.c etc so we could reduce the kernel size.
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* Jakub Jelinek (jj@sunsite.mff.cuni.cz)
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* Changed these to btfixup entities... It saves cycles :)
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*/
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BTFIXUPDEF_CALL(void, disable_irq, unsigned int)
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BTFIXUPDEF_CALL(void, enable_irq, unsigned int)
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BTFIXUPDEF_CALL(void, disable_pil_irq, unsigned int)
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BTFIXUPDEF_CALL(void, enable_pil_irq, unsigned int)
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BTFIXUPDEF_CALL(void, clear_clock_irq, void)
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BTFIXUPDEF_CALL(void, clear_profile_irq, int)
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BTFIXUPDEF_CALL(void, load_profile_irq, int, unsigned int)
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static inline void disable_irq_nosync(unsigned int irq)
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{
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BTFIXUP_CALL(disable_irq)(irq);
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}
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static inline void disable_irq(unsigned int irq)
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{
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BTFIXUP_CALL(disable_irq)(irq);
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}
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static inline void enable_irq(unsigned int irq)
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{
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BTFIXUP_CALL(enable_irq)(irq);
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}
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static inline void disable_pil_irq(unsigned int irq)
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{
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BTFIXUP_CALL(disable_pil_irq)(irq);
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}
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static inline void enable_pil_irq(unsigned int irq)
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{
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BTFIXUP_CALL(enable_pil_irq)(irq);
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}
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static inline void clear_clock_irq(void)
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{
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BTFIXUP_CALL(clear_clock_irq)();
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}
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static inline void clear_profile_irq(int irq)
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{
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BTFIXUP_CALL(clear_profile_irq)(irq);
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}
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static inline void load_profile_irq(int cpu, int limit)
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{
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BTFIXUP_CALL(load_profile_irq)(cpu, limit);
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}
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extern void (*sparc_init_timers)(irqreturn_t (*lvl10_irq)(int, void *, struct pt_regs *));
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extern void claim_ticker14(irqreturn_t (*irq_handler)(int, void *, struct pt_regs *),
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int irq,
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unsigned int timeout);
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#ifdef CONFIG_SMP
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BTFIXUPDEF_CALL(void, set_cpu_int, int, int)
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BTFIXUPDEF_CALL(void, clear_cpu_int, int, int)
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BTFIXUPDEF_CALL(void, set_irq_udt, int)
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#define set_cpu_int(cpu,level) BTFIXUP_CALL(set_cpu_int)(cpu,level)
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#define clear_cpu_int(cpu,level) BTFIXUP_CALL(clear_cpu_int)(cpu,level)
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#define set_irq_udt(cpu) BTFIXUP_CALL(set_irq_udt)(cpu)
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#endif
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extern int request_fast_irq(unsigned int irq, irqreturn_t (*handler)(int, void *, struct pt_regs *), unsigned long flags, __const__ char *devname);
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/* On the sun4m, just like the timers, we have both per-cpu and master
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* interrupt registers.
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*/
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/* These registers are used for sending/receiving irqs from/to
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* different cpu's.
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*/
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struct sun4m_intreg_percpu {
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unsigned int tbt; /* Interrupts still pending for this cpu. */
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/* These next two registers are WRITE-ONLY and are only
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* "on bit" sensitive, "off bits" written have NO affect.
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*/
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unsigned int clear; /* Clear this cpus irqs here. */
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unsigned int set; /* Set this cpus irqs here. */
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unsigned char space[PAGE_SIZE - 12];
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};
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/*
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* djhr
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* Actually the clear and set fields in this struct are misleading..
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* according to the SLAVIO manual (and the same applies for the SEC)
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* the clear field clears bits in the mask which will ENABLE that IRQ
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* the set field sets bits in the mask to DISABLE the IRQ.
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*
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* Also the undirected_xx address in the SLAVIO is defined as
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* RESERVED and write only..
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*
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* DAVEM_NOTE: The SLAVIO only specifies behavior on uniprocessor
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* sun4m machines, for MP the layout makes more sense.
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*/
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struct sun4m_intregs {
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struct sun4m_intreg_percpu cpu_intregs[SUN4M_NCPUS];
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unsigned int tbt; /* IRQ's that are still pending. */
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unsigned int irqs; /* Master IRQ bits. */
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/* Again, like the above, two these registers are WRITE-ONLY. */
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unsigned int clear; /* Clear master IRQ's by setting bits here. */
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unsigned int set; /* Set master IRQ's by setting bits here. */
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/* This register is both READ and WRITE. */
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unsigned int undirected_target; /* Which cpu gets undirected irqs. */
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};
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extern struct sun4m_intregs *sun4m_interrupts;
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/*
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* Bit field defines for the interrupt registers on various
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* Sparc machines.
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*/
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/* The sun4c interrupt register. */
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#define SUN4C_INT_ENABLE 0x01 /* Allow interrupts. */
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#define SUN4C_INT_E14 0x80 /* Enable level 14 IRQ. */
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#define SUN4C_INT_E10 0x20 /* Enable level 10 IRQ. */
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#define SUN4C_INT_E8 0x10 /* Enable level 8 IRQ. */
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#define SUN4C_INT_E6 0x08 /* Enable level 6 IRQ. */
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#define SUN4C_INT_E4 0x04 /* Enable level 4 IRQ. */
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#define SUN4C_INT_E1 0x02 /* Enable level 1 IRQ. */
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/* Dave Redman (djhr@tadpole.co.uk)
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* The sun4m interrupt registers.
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*/
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#define SUN4M_INT_ENABLE 0x80000000
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#define SUN4M_INT_E14 0x00000080
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#define SUN4M_INT_E10 0x00080000
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#define SUN4M_HARD_INT(x) (0x000000001 << (x))
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#define SUN4M_SOFT_INT(x) (0x000010000 << (x))
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#define SUN4M_INT_MASKALL 0x80000000 /* mask all interrupts */
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#define SUN4M_INT_MODULE_ERR 0x40000000 /* module error */
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#define SUN4M_INT_M2S_WRITE 0x20000000 /* write buffer error */
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#define SUN4M_INT_ECC 0x10000000 /* ecc memory error */
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#define SUN4M_INT_FLOPPY 0x00400000 /* floppy disk */
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#define SUN4M_INT_MODULE 0x00200000 /* module interrupt */
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#define SUN4M_INT_VIDEO 0x00100000 /* onboard video */
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#define SUN4M_INT_REALTIME 0x00080000 /* system timer */
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#define SUN4M_INT_SCSI 0x00040000 /* onboard scsi */
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#define SUN4M_INT_AUDIO 0x00020000 /* audio/isdn */
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#define SUN4M_INT_ETHERNET 0x00010000 /* onboard ethernet */
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#define SUN4M_INT_SERIAL 0x00008000 /* serial ports */
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#define SUN4M_INT_KBDMS 0x00004000 /* keyboard/mouse */
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#define SUN4M_INT_SBUSBITS 0x00003F80 /* sbus int bits */
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#define SUN4M_INT_SBUS(x) (1 << (x+7))
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#define SUN4M_INT_VME(x) (1 << (x))
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#endif
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