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fe765aeb77
Split posting WQEs logic to helpers, generalize it and expose for future use in the UMR post send. Link: https://lore.kernel.org/r/a2b0f6cd96f0405a65d38e82c6ae7ef34dcb34bc.1649747695.git.leonro@nvidia.com Signed-off-by: Aharon Landau <aharonl@nvidia.com> Reviewed-by: Michael Guralnik <michaelgur@nvidia.com> Signed-off-by: Leon Romanovsky <leonro@nvidia.com> Signed-off-by: Jason Gunthorpe <jgg@nvidia.com>
137 lines
4.0 KiB
C
137 lines
4.0 KiB
C
/* SPDX-License-Identifier: GPL-2.0 OR Linux-OpenIB */
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/*
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* Copyright (c) 2020, Mellanox Technologies inc. All rights reserved.
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*/
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#ifndef _MLX5_IB_WR_H
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#define _MLX5_IB_WR_H
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#include "mlx5_ib.h"
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enum {
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MLX5_IB_SQ_UMR_INLINE_THRESHOLD = 64,
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};
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struct mlx5_wqe_eth_pad {
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u8 rsvd0[16];
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};
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/* get_sq_edge - Get the next nearby edge.
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*
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* An 'edge' is defined as the first following address after the end
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* of the fragment or the SQ. Accordingly, during the WQE construction
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* which repetitively increases the pointer to write the next data, it
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* simply should check if it gets to an edge.
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*
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* @sq - SQ buffer.
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* @idx - Stride index in the SQ buffer.
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*
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* Return:
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* The new edge.
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*/
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static inline void *get_sq_edge(struct mlx5_ib_wq *sq, u32 idx)
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{
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void *fragment_end;
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fragment_end = mlx5_frag_buf_get_wqe
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(&sq->fbc,
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mlx5_frag_buf_get_idx_last_contig_stride(&sq->fbc, idx));
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return fragment_end + MLX5_SEND_WQE_BB;
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}
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/* handle_post_send_edge - Check if we get to SQ edge. If yes, update to the
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* next nearby edge and get new address translation for current WQE position.
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* @sq: SQ buffer.
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* @seg: Current WQE position (16B aligned).
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* @wqe_sz: Total current WQE size [16B].
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* @cur_edge: Updated current edge.
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*/
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static inline void handle_post_send_edge(struct mlx5_ib_wq *sq, void **seg,
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u32 wqe_sz, void **cur_edge)
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{
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u32 idx;
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if (likely(*seg != *cur_edge))
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return;
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idx = (sq->cur_post + (wqe_sz >> 2)) & (sq->wqe_cnt - 1);
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*cur_edge = get_sq_edge(sq, idx);
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*seg = mlx5_frag_buf_get_wqe(&sq->fbc, idx);
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}
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/* mlx5r_memcpy_send_wqe - copy data from src to WQE and update the relevant
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* WQ's pointers. At the end @seg is aligned to 16B regardless the copied size.
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* @sq: SQ buffer.
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* @cur_edge: Updated current edge.
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* @seg: Current WQE position (16B aligned).
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* @wqe_sz: Total current WQE size [16B].
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* @src: Pointer to copy from.
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* @n: Number of bytes to copy.
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*/
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static inline void mlx5r_memcpy_send_wqe(struct mlx5_ib_wq *sq, void **cur_edge,
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void **seg, u32 *wqe_sz,
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const void *src, size_t n)
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{
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while (likely(n)) {
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size_t leftlen = *cur_edge - *seg;
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size_t copysz = min_t(size_t, leftlen, n);
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size_t stride;
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memcpy(*seg, src, copysz);
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n -= copysz;
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src += copysz;
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stride = !n ? ALIGN(copysz, 16) : copysz;
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*seg += stride;
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*wqe_sz += stride >> 4;
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handle_post_send_edge(sq, seg, *wqe_sz, cur_edge);
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}
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}
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int mlx5r_wq_overflow(struct mlx5_ib_wq *wq, int nreq, struct ib_cq *ib_cq);
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int mlx5r_begin_wqe(struct mlx5_ib_qp *qp, void **seg,
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struct mlx5_wqe_ctrl_seg **ctrl, unsigned int *idx,
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int *size, void **cur_edge, int nreq, __be32 general_id,
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bool send_signaled, bool solicited);
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void mlx5r_finish_wqe(struct mlx5_ib_qp *qp, struct mlx5_wqe_ctrl_seg *ctrl,
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void *seg, u8 size, void *cur_edge, unsigned int idx,
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u64 wr_id, int nreq, u8 fence, u32 mlx5_opcode);
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void mlx5r_ring_db(struct mlx5_ib_qp *qp, unsigned int nreq,
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struct mlx5_wqe_ctrl_seg *ctrl);
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int mlx5_ib_post_send(struct ib_qp *ibqp, const struct ib_send_wr *wr,
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const struct ib_send_wr **bad_wr, bool drain);
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int mlx5_ib_post_recv(struct ib_qp *ibqp, const struct ib_recv_wr *wr,
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const struct ib_recv_wr **bad_wr, bool drain);
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static inline int mlx5_ib_post_send_nodrain(struct ib_qp *ibqp,
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const struct ib_send_wr *wr,
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const struct ib_send_wr **bad_wr)
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{
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return mlx5_ib_post_send(ibqp, wr, bad_wr, false);
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}
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static inline int mlx5_ib_post_send_drain(struct ib_qp *ibqp,
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const struct ib_send_wr *wr,
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const struct ib_send_wr **bad_wr)
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{
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return mlx5_ib_post_send(ibqp, wr, bad_wr, true);
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}
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static inline int mlx5_ib_post_recv_nodrain(struct ib_qp *ibqp,
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const struct ib_recv_wr *wr,
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const struct ib_recv_wr **bad_wr)
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{
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return mlx5_ib_post_recv(ibqp, wr, bad_wr, false);
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}
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static inline int mlx5_ib_post_recv_drain(struct ib_qp *ibqp,
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const struct ib_recv_wr *wr,
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const struct ib_recv_wr **bad_wr)
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{
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return mlx5_ib_post_recv(ibqp, wr, bad_wr, true);
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}
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#endif /* _MLX5_IB_WR_H */
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