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31803e5923
mlx5_core_create_{cq/dct} functions are non-trivial mlx5 commands functions. They check command execution status themselves and hide valuable FW failure information. For mlx5_core/eth kernel user this is what we actually want, but for a devx/rdma user the hidden information is essential and should be propagated up to the caller, thus we convert these commands to use mlx5_cmd_do to return the FW/driver and command outbox status as is, and let the caller decide what to do with it. For kernel callers of mlx5_core_create_{cq/dct} or those who only care about the binary status (FAIL/SUCCESS) they must check status themselves via mlx5_cmd_check() to restore the current behavior. err = mlx5_create_cq(in, out) err = mlx5_cmd_check(err, in, out) if (err) // handle err For DEVX users and those who care about full visibility, They will just propagate the error to user space, and app can check if err == -EREMOTEIO, then outbox.{status,syndrome} are valid. API Note: mlx5_cmd_check() must be used by kernel users since it allows the driver to intercept the command execution status and return a driver simulated status in case of driver induced error handling or reset/recovery flows. Signed-off-by: Saeed Mahameed <saeedm@mellanox.com> Signed-off-by: Saeed Mahameed <saeedm@nvidia.com>
649 lines
16 KiB
C
649 lines
16 KiB
C
// SPDX-License-Identifier: GPL-2.0 OR Linux-OpenIB
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/*
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* Copyright (c) 2013-2020, Mellanox Technologies inc. All rights reserved.
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*/
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#include <linux/gfp.h>
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#include <linux/mlx5/qp.h>
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#include <linux/mlx5/driver.h>
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#include "mlx5_ib.h"
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#include "qp.h"
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static int mlx5_core_drain_dct(struct mlx5_ib_dev *dev,
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struct mlx5_core_dct *dct);
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static struct mlx5_core_rsc_common *
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mlx5_get_rsc(struct mlx5_qp_table *table, u32 rsn)
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{
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struct mlx5_core_rsc_common *common;
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unsigned long flags;
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spin_lock_irqsave(&table->lock, flags);
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common = radix_tree_lookup(&table->tree, rsn);
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if (common)
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refcount_inc(&common->refcount);
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spin_unlock_irqrestore(&table->lock, flags);
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return common;
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}
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void mlx5_core_put_rsc(struct mlx5_core_rsc_common *common)
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{
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if (refcount_dec_and_test(&common->refcount))
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complete(&common->free);
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}
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static u64 qp_allowed_event_types(void)
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{
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u64 mask;
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mask = BIT(MLX5_EVENT_TYPE_PATH_MIG) |
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BIT(MLX5_EVENT_TYPE_COMM_EST) |
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BIT(MLX5_EVENT_TYPE_SQ_DRAINED) |
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BIT(MLX5_EVENT_TYPE_SRQ_LAST_WQE) |
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BIT(MLX5_EVENT_TYPE_WQ_CATAS_ERROR) |
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BIT(MLX5_EVENT_TYPE_PATH_MIG_FAILED) |
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BIT(MLX5_EVENT_TYPE_WQ_INVAL_REQ_ERROR) |
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BIT(MLX5_EVENT_TYPE_WQ_ACCESS_ERROR);
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return mask;
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}
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static u64 rq_allowed_event_types(void)
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{
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u64 mask;
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mask = BIT(MLX5_EVENT_TYPE_SRQ_LAST_WQE) |
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BIT(MLX5_EVENT_TYPE_WQ_CATAS_ERROR);
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return mask;
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}
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static u64 sq_allowed_event_types(void)
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{
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return BIT(MLX5_EVENT_TYPE_WQ_CATAS_ERROR);
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}
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static u64 dct_allowed_event_types(void)
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{
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return BIT(MLX5_EVENT_TYPE_DCT_DRAINED);
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}
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static bool is_event_type_allowed(int rsc_type, int event_type)
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{
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switch (rsc_type) {
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case MLX5_EVENT_QUEUE_TYPE_QP:
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return BIT(event_type) & qp_allowed_event_types();
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case MLX5_EVENT_QUEUE_TYPE_RQ:
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return BIT(event_type) & rq_allowed_event_types();
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case MLX5_EVENT_QUEUE_TYPE_SQ:
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return BIT(event_type) & sq_allowed_event_types();
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case MLX5_EVENT_QUEUE_TYPE_DCT:
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return BIT(event_type) & dct_allowed_event_types();
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default:
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WARN(1, "Event arrived for unknown resource type");
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return false;
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}
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}
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static int rsc_event_notifier(struct notifier_block *nb,
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unsigned long type, void *data)
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{
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struct mlx5_core_rsc_common *common;
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struct mlx5_qp_table *table;
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struct mlx5_core_dct *dct;
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u8 event_type = (u8)type;
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struct mlx5_core_qp *qp;
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struct mlx5_eqe *eqe;
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u32 rsn;
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switch (event_type) {
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case MLX5_EVENT_TYPE_DCT_DRAINED:
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eqe = data;
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rsn = be32_to_cpu(eqe->data.dct.dctn) & 0xffffff;
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rsn |= (MLX5_RES_DCT << MLX5_USER_INDEX_LEN);
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break;
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case MLX5_EVENT_TYPE_PATH_MIG:
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case MLX5_EVENT_TYPE_COMM_EST:
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case MLX5_EVENT_TYPE_SQ_DRAINED:
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case MLX5_EVENT_TYPE_SRQ_LAST_WQE:
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case MLX5_EVENT_TYPE_WQ_CATAS_ERROR:
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case MLX5_EVENT_TYPE_PATH_MIG_FAILED:
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case MLX5_EVENT_TYPE_WQ_INVAL_REQ_ERROR:
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case MLX5_EVENT_TYPE_WQ_ACCESS_ERROR:
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eqe = data;
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rsn = be32_to_cpu(eqe->data.qp_srq.qp_srq_n) & 0xffffff;
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rsn |= (eqe->data.qp_srq.type << MLX5_USER_INDEX_LEN);
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break;
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default:
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return NOTIFY_DONE;
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}
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table = container_of(nb, struct mlx5_qp_table, nb);
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common = mlx5_get_rsc(table, rsn);
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if (!common)
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return NOTIFY_OK;
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if (!is_event_type_allowed((rsn >> MLX5_USER_INDEX_LEN), event_type))
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goto out;
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switch (common->res) {
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case MLX5_RES_QP:
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case MLX5_RES_RQ:
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case MLX5_RES_SQ:
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qp = (struct mlx5_core_qp *)common;
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qp->event(qp, event_type);
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break;
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case MLX5_RES_DCT:
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dct = (struct mlx5_core_dct *)common;
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if (event_type == MLX5_EVENT_TYPE_DCT_DRAINED)
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complete(&dct->drained);
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break;
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default:
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break;
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}
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out:
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mlx5_core_put_rsc(common);
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return NOTIFY_OK;
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}
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static int create_resource_common(struct mlx5_ib_dev *dev,
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struct mlx5_core_qp *qp, int rsc_type)
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{
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struct mlx5_qp_table *table = &dev->qp_table;
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int err;
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qp->common.res = rsc_type;
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spin_lock_irq(&table->lock);
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err = radix_tree_insert(&table->tree,
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qp->qpn | (rsc_type << MLX5_USER_INDEX_LEN),
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qp);
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spin_unlock_irq(&table->lock);
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if (err)
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return err;
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refcount_set(&qp->common.refcount, 1);
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init_completion(&qp->common.free);
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qp->pid = current->pid;
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return 0;
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}
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static void destroy_resource_common(struct mlx5_ib_dev *dev,
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struct mlx5_core_qp *qp)
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{
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struct mlx5_qp_table *table = &dev->qp_table;
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unsigned long flags;
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spin_lock_irqsave(&table->lock, flags);
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radix_tree_delete(&table->tree,
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qp->qpn | (qp->common.res << MLX5_USER_INDEX_LEN));
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spin_unlock_irqrestore(&table->lock, flags);
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mlx5_core_put_rsc((struct mlx5_core_rsc_common *)qp);
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wait_for_completion(&qp->common.free);
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}
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static int _mlx5_core_destroy_dct(struct mlx5_ib_dev *dev,
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struct mlx5_core_dct *dct, bool need_cleanup)
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{
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u32 in[MLX5_ST_SZ_DW(destroy_dct_in)] = {};
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struct mlx5_core_qp *qp = &dct->mqp;
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int err;
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err = mlx5_core_drain_dct(dev, dct);
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if (err) {
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if (dev->mdev->state == MLX5_DEVICE_STATE_INTERNAL_ERROR)
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goto destroy;
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return err;
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}
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wait_for_completion(&dct->drained);
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destroy:
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if (need_cleanup)
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destroy_resource_common(dev, &dct->mqp);
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MLX5_SET(destroy_dct_in, in, opcode, MLX5_CMD_OP_DESTROY_DCT);
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MLX5_SET(destroy_dct_in, in, dctn, qp->qpn);
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MLX5_SET(destroy_dct_in, in, uid, qp->uid);
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err = mlx5_cmd_exec_in(dev->mdev, destroy_dct, in);
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return err;
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}
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int mlx5_core_create_dct(struct mlx5_ib_dev *dev, struct mlx5_core_dct *dct,
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u32 *in, int inlen, u32 *out, int outlen)
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{
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struct mlx5_core_qp *qp = &dct->mqp;
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int err;
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init_completion(&dct->drained);
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MLX5_SET(create_dct_in, in, opcode, MLX5_CMD_OP_CREATE_DCT);
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err = mlx5_cmd_do(dev->mdev, in, inlen, out, outlen);
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if (err)
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return err;
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qp->qpn = MLX5_GET(create_dct_out, out, dctn);
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qp->uid = MLX5_GET(create_dct_in, in, uid);
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err = create_resource_common(dev, qp, MLX5_RES_DCT);
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if (err)
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goto err_cmd;
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return 0;
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err_cmd:
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_mlx5_core_destroy_dct(dev, dct, false);
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return err;
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}
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int mlx5_qpc_create_qp(struct mlx5_ib_dev *dev, struct mlx5_core_qp *qp,
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u32 *in, int inlen, u32 *out)
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{
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u32 din[MLX5_ST_SZ_DW(destroy_qp_in)] = {};
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int err;
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MLX5_SET(create_qp_in, in, opcode, MLX5_CMD_OP_CREATE_QP);
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err = mlx5_cmd_exec(dev->mdev, in, inlen, out,
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MLX5_ST_SZ_BYTES(create_qp_out));
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if (err)
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return err;
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qp->uid = MLX5_GET(create_qp_in, in, uid);
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qp->qpn = MLX5_GET(create_qp_out, out, qpn);
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err = create_resource_common(dev, qp, MLX5_RES_QP);
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if (err)
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goto err_cmd;
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mlx5_debug_qp_add(dev->mdev, qp);
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return 0;
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err_cmd:
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MLX5_SET(destroy_qp_in, din, opcode, MLX5_CMD_OP_DESTROY_QP);
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MLX5_SET(destroy_qp_in, din, qpn, qp->qpn);
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MLX5_SET(destroy_qp_in, din, uid, qp->uid);
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mlx5_cmd_exec_in(dev->mdev, destroy_qp, din);
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return err;
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}
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static int mlx5_core_drain_dct(struct mlx5_ib_dev *dev,
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struct mlx5_core_dct *dct)
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{
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u32 in[MLX5_ST_SZ_DW(drain_dct_in)] = {};
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struct mlx5_core_qp *qp = &dct->mqp;
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MLX5_SET(drain_dct_in, in, opcode, MLX5_CMD_OP_DRAIN_DCT);
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MLX5_SET(drain_dct_in, in, dctn, qp->qpn);
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MLX5_SET(drain_dct_in, in, uid, qp->uid);
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return mlx5_cmd_exec_in(dev->mdev, drain_dct, in);
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}
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int mlx5_core_destroy_dct(struct mlx5_ib_dev *dev,
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struct mlx5_core_dct *dct)
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{
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return _mlx5_core_destroy_dct(dev, dct, true);
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}
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int mlx5_core_destroy_qp(struct mlx5_ib_dev *dev, struct mlx5_core_qp *qp)
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{
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u32 in[MLX5_ST_SZ_DW(destroy_qp_in)] = {};
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mlx5_debug_qp_remove(dev->mdev, qp);
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destroy_resource_common(dev, qp);
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MLX5_SET(destroy_qp_in, in, opcode, MLX5_CMD_OP_DESTROY_QP);
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MLX5_SET(destroy_qp_in, in, qpn, qp->qpn);
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MLX5_SET(destroy_qp_in, in, uid, qp->uid);
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mlx5_cmd_exec_in(dev->mdev, destroy_qp, in);
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return 0;
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}
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int mlx5_core_set_delay_drop(struct mlx5_ib_dev *dev,
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u32 timeout_usec)
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{
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u32 in[MLX5_ST_SZ_DW(set_delay_drop_params_in)] = {};
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MLX5_SET(set_delay_drop_params_in, in, opcode,
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MLX5_CMD_OP_SET_DELAY_DROP_PARAMS);
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MLX5_SET(set_delay_drop_params_in, in, delay_drop_timeout,
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timeout_usec / 100);
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return mlx5_cmd_exec_in(dev->mdev, set_delay_drop_params, in);
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}
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struct mbox_info {
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u32 *in;
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u32 *out;
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int inlen;
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int outlen;
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};
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static int mbox_alloc(struct mbox_info *mbox, int inlen, int outlen)
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{
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mbox->inlen = inlen;
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mbox->outlen = outlen;
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mbox->in = kzalloc(mbox->inlen, GFP_KERNEL);
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mbox->out = kzalloc(mbox->outlen, GFP_KERNEL);
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if (!mbox->in || !mbox->out) {
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kfree(mbox->in);
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kfree(mbox->out);
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return -ENOMEM;
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}
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return 0;
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}
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static void mbox_free(struct mbox_info *mbox)
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{
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kfree(mbox->in);
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kfree(mbox->out);
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}
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static int get_ece_from_mbox(void *out, u16 opcode)
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{
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int ece = 0;
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switch (opcode) {
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case MLX5_CMD_OP_INIT2INIT_QP:
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ece = MLX5_GET(init2init_qp_out, out, ece);
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break;
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case MLX5_CMD_OP_INIT2RTR_QP:
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ece = MLX5_GET(init2rtr_qp_out, out, ece);
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break;
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case MLX5_CMD_OP_RTR2RTS_QP:
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ece = MLX5_GET(rtr2rts_qp_out, out, ece);
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break;
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case MLX5_CMD_OP_RTS2RTS_QP:
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ece = MLX5_GET(rts2rts_qp_out, out, ece);
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break;
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case MLX5_CMD_OP_RST2INIT_QP:
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ece = MLX5_GET(rst2init_qp_out, out, ece);
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break;
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default:
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break;
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}
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return ece;
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}
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static int modify_qp_mbox_alloc(struct mlx5_core_dev *dev, u16 opcode, int qpn,
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u32 opt_param_mask, void *qpc,
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struct mbox_info *mbox, u16 uid, u32 ece)
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{
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mbox->out = NULL;
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mbox->in = NULL;
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#define MBOX_ALLOC(mbox, typ) \
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mbox_alloc(mbox, MLX5_ST_SZ_BYTES(typ##_in), MLX5_ST_SZ_BYTES(typ##_out))
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#define MOD_QP_IN_SET(typ, in, _opcode, _qpn, _uid) \
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do { \
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MLX5_SET(typ##_in, in, opcode, _opcode); \
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MLX5_SET(typ##_in, in, qpn, _qpn); \
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MLX5_SET(typ##_in, in, uid, _uid); \
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} while (0)
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#define MOD_QP_IN_SET_QPC(typ, in, _opcode, _qpn, _opt_p, _qpc, _uid) \
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do { \
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MOD_QP_IN_SET(typ, in, _opcode, _qpn, _uid); \
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MLX5_SET(typ##_in, in, opt_param_mask, _opt_p); \
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memcpy(MLX5_ADDR_OF(typ##_in, in, qpc), _qpc, \
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MLX5_ST_SZ_BYTES(qpc)); \
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} while (0)
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switch (opcode) {
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/* 2RST & 2ERR */
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case MLX5_CMD_OP_2RST_QP:
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if (MBOX_ALLOC(mbox, qp_2rst))
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return -ENOMEM;
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MOD_QP_IN_SET(qp_2rst, mbox->in, opcode, qpn, uid);
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break;
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case MLX5_CMD_OP_2ERR_QP:
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if (MBOX_ALLOC(mbox, qp_2err))
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return -ENOMEM;
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MOD_QP_IN_SET(qp_2err, mbox->in, opcode, qpn, uid);
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break;
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/* MODIFY with QPC */
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case MLX5_CMD_OP_RST2INIT_QP:
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if (MBOX_ALLOC(mbox, rst2init_qp))
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return -ENOMEM;
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MOD_QP_IN_SET_QPC(rst2init_qp, mbox->in, opcode, qpn,
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opt_param_mask, qpc, uid);
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MLX5_SET(rst2init_qp_in, mbox->in, ece, ece);
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break;
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case MLX5_CMD_OP_INIT2RTR_QP:
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if (MBOX_ALLOC(mbox, init2rtr_qp))
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return -ENOMEM;
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MOD_QP_IN_SET_QPC(init2rtr_qp, mbox->in, opcode, qpn,
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opt_param_mask, qpc, uid);
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MLX5_SET(init2rtr_qp_in, mbox->in, ece, ece);
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break;
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case MLX5_CMD_OP_RTR2RTS_QP:
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if (MBOX_ALLOC(mbox, rtr2rts_qp))
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return -ENOMEM;
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MOD_QP_IN_SET_QPC(rtr2rts_qp, mbox->in, opcode, qpn,
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opt_param_mask, qpc, uid);
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MLX5_SET(rtr2rts_qp_in, mbox->in, ece, ece);
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break;
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case MLX5_CMD_OP_RTS2RTS_QP:
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if (MBOX_ALLOC(mbox, rts2rts_qp))
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return -ENOMEM;
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MOD_QP_IN_SET_QPC(rts2rts_qp, mbox->in, opcode, qpn,
|
|
opt_param_mask, qpc, uid);
|
|
MLX5_SET(rts2rts_qp_in, mbox->in, ece, ece);
|
|
break;
|
|
case MLX5_CMD_OP_SQERR2RTS_QP:
|
|
if (MBOX_ALLOC(mbox, sqerr2rts_qp))
|
|
return -ENOMEM;
|
|
MOD_QP_IN_SET_QPC(sqerr2rts_qp, mbox->in, opcode, qpn,
|
|
opt_param_mask, qpc, uid);
|
|
break;
|
|
case MLX5_CMD_OP_SQD_RTS_QP:
|
|
if (MBOX_ALLOC(mbox, sqd2rts_qp))
|
|
return -ENOMEM;
|
|
MOD_QP_IN_SET_QPC(sqd2rts_qp, mbox->in, opcode, qpn,
|
|
opt_param_mask, qpc, uid);
|
|
break;
|
|
case MLX5_CMD_OP_INIT2INIT_QP:
|
|
if (MBOX_ALLOC(mbox, init2init_qp))
|
|
return -ENOMEM;
|
|
MOD_QP_IN_SET_QPC(init2init_qp, mbox->in, opcode, qpn,
|
|
opt_param_mask, qpc, uid);
|
|
MLX5_SET(init2init_qp_in, mbox->in, ece, ece);
|
|
break;
|
|
default:
|
|
return -EINVAL;
|
|
}
|
|
return 0;
|
|
}
|
|
|
|
int mlx5_core_qp_modify(struct mlx5_ib_dev *dev, u16 opcode, u32 opt_param_mask,
|
|
void *qpc, struct mlx5_core_qp *qp, u32 *ece)
|
|
{
|
|
struct mbox_info mbox;
|
|
int err;
|
|
|
|
err = modify_qp_mbox_alloc(dev->mdev, opcode, qp->qpn, opt_param_mask,
|
|
qpc, &mbox, qp->uid, (ece) ? *ece : 0);
|
|
if (err)
|
|
return err;
|
|
|
|
err = mlx5_cmd_exec(dev->mdev, mbox.in, mbox.inlen, mbox.out,
|
|
mbox.outlen);
|
|
|
|
if (ece)
|
|
*ece = get_ece_from_mbox(mbox.out, opcode);
|
|
|
|
mbox_free(&mbox);
|
|
return err;
|
|
}
|
|
|
|
int mlx5_init_qp_table(struct mlx5_ib_dev *dev)
|
|
{
|
|
struct mlx5_qp_table *table = &dev->qp_table;
|
|
|
|
spin_lock_init(&table->lock);
|
|
INIT_RADIX_TREE(&table->tree, GFP_ATOMIC);
|
|
mlx5_qp_debugfs_init(dev->mdev);
|
|
|
|
table->nb.notifier_call = rsc_event_notifier;
|
|
mlx5_notifier_register(dev->mdev, &table->nb);
|
|
|
|
return 0;
|
|
}
|
|
|
|
void mlx5_cleanup_qp_table(struct mlx5_ib_dev *dev)
|
|
{
|
|
struct mlx5_qp_table *table = &dev->qp_table;
|
|
|
|
mlx5_notifier_unregister(dev->mdev, &table->nb);
|
|
mlx5_qp_debugfs_cleanup(dev->mdev);
|
|
}
|
|
|
|
int mlx5_core_qp_query(struct mlx5_ib_dev *dev, struct mlx5_core_qp *qp,
|
|
u32 *out, int outlen)
|
|
{
|
|
u32 in[MLX5_ST_SZ_DW(query_qp_in)] = {};
|
|
|
|
MLX5_SET(query_qp_in, in, opcode, MLX5_CMD_OP_QUERY_QP);
|
|
MLX5_SET(query_qp_in, in, qpn, qp->qpn);
|
|
return mlx5_cmd_exec(dev->mdev, in, sizeof(in), out, outlen);
|
|
}
|
|
|
|
int mlx5_core_dct_query(struct mlx5_ib_dev *dev, struct mlx5_core_dct *dct,
|
|
u32 *out, int outlen)
|
|
{
|
|
u32 in[MLX5_ST_SZ_DW(query_dct_in)] = {};
|
|
struct mlx5_core_qp *qp = &dct->mqp;
|
|
|
|
MLX5_SET(query_dct_in, in, opcode, MLX5_CMD_OP_QUERY_DCT);
|
|
MLX5_SET(query_dct_in, in, dctn, qp->qpn);
|
|
|
|
return mlx5_cmd_exec(dev->mdev, (void *)&in, sizeof(in), (void *)out,
|
|
outlen);
|
|
}
|
|
|
|
int mlx5_core_xrcd_alloc(struct mlx5_ib_dev *dev, u32 *xrcdn)
|
|
{
|
|
u32 out[MLX5_ST_SZ_DW(alloc_xrcd_out)] = {};
|
|
u32 in[MLX5_ST_SZ_DW(alloc_xrcd_in)] = {};
|
|
int err;
|
|
|
|
MLX5_SET(alloc_xrcd_in, in, opcode, MLX5_CMD_OP_ALLOC_XRCD);
|
|
err = mlx5_cmd_exec_inout(dev->mdev, alloc_xrcd, in, out);
|
|
if (!err)
|
|
*xrcdn = MLX5_GET(alloc_xrcd_out, out, xrcd);
|
|
return err;
|
|
}
|
|
|
|
int mlx5_core_xrcd_dealloc(struct mlx5_ib_dev *dev, u32 xrcdn)
|
|
{
|
|
u32 in[MLX5_ST_SZ_DW(dealloc_xrcd_in)] = {};
|
|
|
|
MLX5_SET(dealloc_xrcd_in, in, opcode, MLX5_CMD_OP_DEALLOC_XRCD);
|
|
MLX5_SET(dealloc_xrcd_in, in, xrcd, xrcdn);
|
|
return mlx5_cmd_exec_in(dev->mdev, dealloc_xrcd, in);
|
|
}
|
|
|
|
static void destroy_rq_tracked(struct mlx5_ib_dev *dev, u32 rqn, u16 uid)
|
|
{
|
|
u32 in[MLX5_ST_SZ_DW(destroy_rq_in)] = {};
|
|
|
|
MLX5_SET(destroy_rq_in, in, opcode, MLX5_CMD_OP_DESTROY_RQ);
|
|
MLX5_SET(destroy_rq_in, in, rqn, rqn);
|
|
MLX5_SET(destroy_rq_in, in, uid, uid);
|
|
mlx5_cmd_exec_in(dev->mdev, destroy_rq, in);
|
|
}
|
|
|
|
int mlx5_core_create_rq_tracked(struct mlx5_ib_dev *dev, u32 *in, int inlen,
|
|
struct mlx5_core_qp *rq)
|
|
{
|
|
int err;
|
|
u32 rqn;
|
|
|
|
err = mlx5_core_create_rq(dev->mdev, in, inlen, &rqn);
|
|
if (err)
|
|
return err;
|
|
|
|
rq->uid = MLX5_GET(create_rq_in, in, uid);
|
|
rq->qpn = rqn;
|
|
err = create_resource_common(dev, rq, MLX5_RES_RQ);
|
|
if (err)
|
|
goto err_destroy_rq;
|
|
|
|
return 0;
|
|
|
|
err_destroy_rq:
|
|
destroy_rq_tracked(dev, rq->qpn, rq->uid);
|
|
|
|
return err;
|
|
}
|
|
|
|
int mlx5_core_destroy_rq_tracked(struct mlx5_ib_dev *dev,
|
|
struct mlx5_core_qp *rq)
|
|
{
|
|
destroy_resource_common(dev, rq);
|
|
destroy_rq_tracked(dev, rq->qpn, rq->uid);
|
|
return 0;
|
|
}
|
|
|
|
static void destroy_sq_tracked(struct mlx5_ib_dev *dev, u32 sqn, u16 uid)
|
|
{
|
|
u32 in[MLX5_ST_SZ_DW(destroy_sq_in)] = {};
|
|
|
|
MLX5_SET(destroy_sq_in, in, opcode, MLX5_CMD_OP_DESTROY_SQ);
|
|
MLX5_SET(destroy_sq_in, in, sqn, sqn);
|
|
MLX5_SET(destroy_sq_in, in, uid, uid);
|
|
mlx5_cmd_exec_in(dev->mdev, destroy_sq, in);
|
|
}
|
|
|
|
int mlx5_core_create_sq_tracked(struct mlx5_ib_dev *dev, u32 *in, int inlen,
|
|
struct mlx5_core_qp *sq)
|
|
{
|
|
u32 out[MLX5_ST_SZ_DW(create_sq_out)] = {};
|
|
int err;
|
|
|
|
MLX5_SET(create_sq_in, in, opcode, MLX5_CMD_OP_CREATE_SQ);
|
|
err = mlx5_cmd_exec(dev->mdev, in, inlen, out, sizeof(out));
|
|
if (err)
|
|
return err;
|
|
|
|
sq->qpn = MLX5_GET(create_sq_out, out, sqn);
|
|
sq->uid = MLX5_GET(create_sq_in, in, uid);
|
|
err = create_resource_common(dev, sq, MLX5_RES_SQ);
|
|
if (err)
|
|
goto err_destroy_sq;
|
|
|
|
return 0;
|
|
|
|
err_destroy_sq:
|
|
destroy_sq_tracked(dev, sq->qpn, sq->uid);
|
|
|
|
return err;
|
|
}
|
|
|
|
void mlx5_core_destroy_sq_tracked(struct mlx5_ib_dev *dev,
|
|
struct mlx5_core_qp *sq)
|
|
{
|
|
destroy_resource_common(dev, sq);
|
|
destroy_sq_tracked(dev, sq->qpn, sq->uid);
|
|
}
|
|
|
|
struct mlx5_core_rsc_common *mlx5_core_res_hold(struct mlx5_ib_dev *dev,
|
|
int res_num,
|
|
enum mlx5_res_type res_type)
|
|
{
|
|
u32 rsn = res_num | (res_type << MLX5_USER_INDEX_LEN);
|
|
struct mlx5_qp_table *table = &dev->qp_table;
|
|
|
|
return mlx5_get_rsc(table, rsn);
|
|
}
|
|
|
|
void mlx5_core_res_put(struct mlx5_core_rsc_common *res)
|
|
{
|
|
mlx5_core_put_rsc(res);
|
|
}
|