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ca7ef7adad
rdma/ib_umem.h and rdma/ib_verbs.h are included by rdma/ib_umem_odp.h. This patch removes the redundant entries. Link: https://lore.kernel.org/r/20220823025131.862811-1-matsuda-daisuke@fujitsu.com Signed-off-by: Daisuke Matsuda <matsuda-daisuke@fujitsu.com> Signed-off-by: Leon Romanovsky <leon@kernel.org>
296 lines
7.6 KiB
C
296 lines
7.6 KiB
C
/*
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* Copyright (c) 2013-2015, Mellanox Technologies. All rights reserved.
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*
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* This software is available to you under a choice of one of two
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* licenses. You may choose to be licensed under the terms of the GNU
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* General Public License (GPL) Version 2, available from the file
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* COPYING in the main directory of this source tree, or the
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* OpenIB.org BSD license below:
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*
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* Redistribution and use in source and binary forms, with or
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* without modification, are permitted provided that the following
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* conditions are met:
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*
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* - Redistributions of source code must retain the above
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* copyright notice, this list of conditions and the following
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* disclaimer.
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*
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* - Redistributions in binary form must reproduce the above
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* copyright notice, this list of conditions and the following
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* disclaimer in the documentation and/or other materials
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* provided with the distribution.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
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* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
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* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
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* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
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* BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
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* ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
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* CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
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* SOFTWARE.
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*/
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#include <rdma/ib_umem_odp.h>
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#include "mlx5_ib.h"
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#include <linux/jiffies.h>
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/*
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* Fill in a physical address list. ib_umem_num_dma_blocks() entries will be
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* filled in the pas array.
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*/
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void mlx5_ib_populate_pas(struct ib_umem *umem, size_t page_size, __be64 *pas,
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u64 access_flags)
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{
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struct ib_block_iter biter;
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rdma_umem_for_each_dma_block (umem, &biter, page_size) {
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*pas = cpu_to_be64(rdma_block_iter_dma_address(&biter) |
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access_flags);
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pas++;
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}
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}
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/*
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* Compute the page shift and page_offset for mailboxes that use a quantized
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* page_offset. The granulatity of the page offset scales according to page
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* size.
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*/
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unsigned long __mlx5_umem_find_best_quantized_pgoff(
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struct ib_umem *umem, unsigned long pgsz_bitmap,
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unsigned int page_offset_bits, u64 pgoff_bitmask, unsigned int scale,
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unsigned int *page_offset_quantized)
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{
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const u64 page_offset_mask = (1UL << page_offset_bits) - 1;
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unsigned long page_size;
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u64 page_offset;
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page_size = ib_umem_find_best_pgoff(umem, pgsz_bitmap, pgoff_bitmask);
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if (!page_size)
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return 0;
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/*
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* page size is the largest possible page size.
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*
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* Reduce the page_size, and thus the page_offset and quanta, until the
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* page_offset fits into the mailbox field. Once page_size < scale this
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* loop is guaranteed to terminate.
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*/
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page_offset = ib_umem_dma_offset(umem, page_size);
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while (page_offset & ~(u64)(page_offset_mask * (page_size / scale))) {
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page_size /= 2;
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page_offset = ib_umem_dma_offset(umem, page_size);
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}
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/*
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* The address is not aligned, or otherwise cannot be represented by the
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* page_offset.
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*/
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if (!(pgsz_bitmap & page_size))
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return 0;
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*page_offset_quantized =
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(unsigned long)page_offset / (page_size / scale);
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if (WARN_ON(*page_offset_quantized > page_offset_mask))
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return 0;
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return page_size;
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}
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#define WR_ID_BF 0xBF
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#define WR_ID_END 0xBAD
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#define TEST_WC_NUM_WQES 255
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#define TEST_WC_POLLING_MAX_TIME_JIFFIES msecs_to_jiffies(100)
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static int post_send_nop(struct mlx5_ib_dev *dev, struct ib_qp *ibqp, u64 wr_id,
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bool signaled)
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{
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struct mlx5_ib_qp *qp = to_mqp(ibqp);
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struct mlx5_wqe_ctrl_seg *ctrl;
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struct mlx5_bf *bf = &qp->bf;
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__be32 mmio_wqe[16] = {};
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unsigned long flags;
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unsigned int idx;
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int i;
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if (unlikely(dev->mdev->state == MLX5_DEVICE_STATE_INTERNAL_ERROR))
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return -EIO;
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spin_lock_irqsave(&qp->sq.lock, flags);
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idx = qp->sq.cur_post & (qp->sq.wqe_cnt - 1);
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ctrl = mlx5_frag_buf_get_wqe(&qp->sq.fbc, idx);
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memset(ctrl, 0, sizeof(struct mlx5_wqe_ctrl_seg));
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ctrl->fm_ce_se = signaled ? MLX5_WQE_CTRL_CQ_UPDATE : 0;
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ctrl->opmod_idx_opcode =
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cpu_to_be32(((u32)(qp->sq.cur_post) << 8) | MLX5_OPCODE_NOP);
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ctrl->qpn_ds = cpu_to_be32((sizeof(struct mlx5_wqe_ctrl_seg) / 16) |
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(qp->trans_qp.base.mqp.qpn << 8));
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qp->sq.wrid[idx] = wr_id;
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qp->sq.w_list[idx].opcode = MLX5_OPCODE_NOP;
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qp->sq.wqe_head[idx] = qp->sq.head + 1;
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qp->sq.cur_post += DIV_ROUND_UP(sizeof(struct mlx5_wqe_ctrl_seg),
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MLX5_SEND_WQE_BB);
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qp->sq.w_list[idx].next = qp->sq.cur_post;
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qp->sq.head++;
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memcpy(mmio_wqe, ctrl, sizeof(*ctrl));
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((struct mlx5_wqe_ctrl_seg *)&mmio_wqe)->fm_ce_se |=
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MLX5_WQE_CTRL_CQ_UPDATE;
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/* Make sure that descriptors are written before
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* updating doorbell record and ringing the doorbell
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*/
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wmb();
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qp->db.db[MLX5_SND_DBR] = cpu_to_be32(qp->sq.cur_post);
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/* Make sure doorbell record is visible to the HCA before
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* we hit doorbell
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*/
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wmb();
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for (i = 0; i < 8; i++)
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mlx5_write64(&mmio_wqe[i * 2],
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bf->bfreg->map + bf->offset + i * 8);
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io_stop_wc();
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bf->offset ^= bf->buf_size;
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spin_unlock_irqrestore(&qp->sq.lock, flags);
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return 0;
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}
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static int test_wc_poll_cq_result(struct mlx5_ib_dev *dev, struct ib_cq *cq)
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{
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int ret;
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struct ib_wc wc = {};
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unsigned long end = jiffies + TEST_WC_POLLING_MAX_TIME_JIFFIES;
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do {
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ret = ib_poll_cq(cq, 1, &wc);
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if (ret < 0 || wc.status)
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return ret < 0 ? ret : -EINVAL;
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if (ret)
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break;
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} while (!time_after(jiffies, end));
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if (!ret)
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return -ETIMEDOUT;
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if (wc.wr_id != WR_ID_BF)
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ret = 0;
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return ret;
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}
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static int test_wc_do_send(struct mlx5_ib_dev *dev, struct ib_qp *qp)
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{
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int err, i;
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for (i = 0; i < TEST_WC_NUM_WQES; i++) {
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err = post_send_nop(dev, qp, WR_ID_BF, false);
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if (err)
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return err;
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}
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return post_send_nop(dev, qp, WR_ID_END, true);
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}
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int mlx5_ib_test_wc(struct mlx5_ib_dev *dev)
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{
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struct ib_cq_init_attr cq_attr = { .cqe = TEST_WC_NUM_WQES + 1 };
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int port_type_cap = MLX5_CAP_GEN(dev->mdev, port_type);
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struct ib_qp_init_attr qp_init_attr = {
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.cap = { .max_send_wr = TEST_WC_NUM_WQES },
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.qp_type = IB_QPT_UD,
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.sq_sig_type = IB_SIGNAL_REQ_WR,
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.create_flags = MLX5_IB_QP_CREATE_WC_TEST,
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};
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struct ib_qp_attr qp_attr = { .port_num = 1 };
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struct ib_device *ibdev = &dev->ib_dev;
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struct ib_qp *qp;
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struct ib_cq *cq;
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struct ib_pd *pd;
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int ret;
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if (!MLX5_CAP_GEN(dev->mdev, bf))
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return 0;
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if (!dev->mdev->roce.roce_en &&
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port_type_cap == MLX5_CAP_PORT_TYPE_ETH) {
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if (mlx5_core_is_pf(dev->mdev))
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dev->wc_support = arch_can_pci_mmap_wc();
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return 0;
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}
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ret = mlx5_alloc_bfreg(dev->mdev, &dev->wc_bfreg, true, false);
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if (ret)
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goto print_err;
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if (!dev->wc_bfreg.wc)
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goto out1;
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pd = ib_alloc_pd(ibdev, 0);
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if (IS_ERR(pd)) {
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ret = PTR_ERR(pd);
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goto out1;
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}
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cq = ib_create_cq(ibdev, NULL, NULL, NULL, &cq_attr);
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if (IS_ERR(cq)) {
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ret = PTR_ERR(cq);
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goto out2;
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}
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qp_init_attr.recv_cq = cq;
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qp_init_attr.send_cq = cq;
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qp = ib_create_qp(pd, &qp_init_attr);
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if (IS_ERR(qp)) {
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ret = PTR_ERR(qp);
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goto out3;
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}
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qp_attr.qp_state = IB_QPS_INIT;
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ret = ib_modify_qp(qp, &qp_attr,
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IB_QP_STATE | IB_QP_PORT | IB_QP_PKEY_INDEX |
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IB_QP_QKEY);
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if (ret)
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goto out4;
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qp_attr.qp_state = IB_QPS_RTR;
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ret = ib_modify_qp(qp, &qp_attr, IB_QP_STATE);
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if (ret)
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goto out4;
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qp_attr.qp_state = IB_QPS_RTS;
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ret = ib_modify_qp(qp, &qp_attr, IB_QP_STATE | IB_QP_SQ_PSN);
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if (ret)
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goto out4;
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ret = test_wc_do_send(dev, qp);
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if (ret < 0)
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goto out4;
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ret = test_wc_poll_cq_result(dev, cq);
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if (ret > 0) {
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dev->wc_support = true;
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ret = 0;
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}
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out4:
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ib_destroy_qp(qp);
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out3:
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ib_destroy_cq(cq);
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out2:
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ib_dealloc_pd(pd);
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out1:
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mlx5_free_bfreg(dev->mdev, &dev->wc_bfreg);
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print_err:
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if (ret)
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mlx5_ib_err(
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dev,
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"Error %d while trying to test write-combining support\n",
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ret);
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return ret;
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}
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