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This commit is a preparation for enabling XUSB SC7 support.
It rearranges Tegra210 XUSB PADCTL UPHY initialization sequence,
for the following reasons:
1. PLLE hardware power sequencer has to be enabled only after both
PEX UPHY PLL and SATA UPHY PLL are initialized.
tegra210_uphy_init() -> tegra210_pex_uphy_enable()
-> tegra210_sata_uphy_enable()
-> tegra210_plle_hw_sequence_start()
-> tegra210_aux_mux_lp0_clamp_disable()
2. At cold boot and SC7 exit, the following bits must be cleared after
PEX/SATA lanes are out of IDDQ (IDDQ_DISABLE=1).
a. XUSB_PADCTL_ELPG_PROGRAM1_AUX_MUX_LP0_CLAMP_EN,
b. XUSB_PADCTL_ELPG_PROGRAM1_AUX_MUX_LP0_CLAMP_EN_EARLY
c. XUSB_PADCTL_ELPG_PROGRAM1_AUX_MUX_LP0_VCORE_DOWN
tegra210_pex_uphy_enable() and tegra210_sata_uphy_enable() are in
charge of bringing lanes out of IDDQ, and then AUX_MUX_LP0_* bits
will be cleared by tegra210_aux_mux_lp0_clamp_disable().
3. Once UPHY PLL hardware power sequencer is enabled, do not assert
reset to PEX/SATA PLLs, otherwise UPHY PLL operation will be broken.
Signed-off-by: JC Kuo <jckuo@nvidia.com>
Acked-By: Vinod Koul <vkoul@kernel.org>
Signed-off-by: Thierry Reding <treding@nvidia.com>
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| .. | ||
| allwinner | ||
| amlogic | ||
| broadcom | ||
| cadence | ||
| freescale | ||
| hisilicon | ||
| ingenic | ||
| intel | ||
| lantiq | ||
| marvell | ||
| mediatek | ||
| microchip | ||
| motorola | ||
| mscc | ||
| qualcomm | ||
| ralink | ||
| renesas | ||
| rockchip | ||
| samsung | ||
| socionext | ||
| st | ||
| tegra | ||
| ti | ||
| xilinx | ||
| Kconfig | ||
| Makefile | ||
| phy-core-mipi-dphy.c | ||
| phy-core.c | ||
| phy-lgm-usb.c | ||
| phy-lpc18xx-usb-otg.c | ||
| phy-pistachio-usb.c | ||
| phy-xgene.c | ||