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03d830e8dc
Much of the HDQ1W integration data is common between multiple generations of OMAP SoCs, so rather than make several copies, we add it once into files which are compiled for multiple SoCs. Signed-off-by: Paul Walmsley <paul@pwsan.com> Cc: NeilBrown <neilb@suse.de> Tested-by: NeilBrown <neilb@suse.de>
327 lines
7.4 KiB
C
327 lines
7.4 KiB
C
/*
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* omap_hwmod_2xxx_3xxx_ipblock_data.c - common IP block data for OMAP2/3
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*
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* Copyright (C) 2011 Nokia Corporation
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* Copyright (C) 2012 Texas Instruments, Inc.
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* Paul Walmsley
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*/
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#include <plat/omap_hwmod.h>
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#include <plat/serial.h>
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#include <plat/dma.h>
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#include <plat/common.h>
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#include <plat/hdq1w.h>
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#include <mach/irqs.h>
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#include "omap_hwmod_common_data.h"
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/* UART */
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static struct omap_hwmod_class_sysconfig omap2_uart_sysc = {
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.rev_offs = 0x50,
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.sysc_offs = 0x54,
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.syss_offs = 0x58,
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.sysc_flags = (SYSC_HAS_SIDLEMODE |
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SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET |
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SYSC_HAS_AUTOIDLE | SYSS_HAS_RESET_STATUS),
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.idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
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.sysc_fields = &omap_hwmod_sysc_type1,
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};
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struct omap_hwmod_class omap2_uart_class = {
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.name = "uart",
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.sysc = &omap2_uart_sysc,
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};
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/*
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* 'dss' class
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* display sub-system
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*/
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static struct omap_hwmod_class_sysconfig omap2_dss_sysc = {
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.rev_offs = 0x0000,
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.sysc_offs = 0x0010,
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.syss_offs = 0x0014,
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.sysc_flags = (SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE |
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SYSS_HAS_RESET_STATUS),
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.sysc_fields = &omap_hwmod_sysc_type1,
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};
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struct omap_hwmod_class omap2_dss_hwmod_class = {
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.name = "dss",
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.sysc = &omap2_dss_sysc,
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.reset = omap_dss_reset,
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};
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/*
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* 'rfbi' class
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* remote frame buffer interface
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*/
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static struct omap_hwmod_class_sysconfig omap2_rfbi_sysc = {
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.rev_offs = 0x0000,
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.sysc_offs = 0x0010,
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.syss_offs = 0x0014,
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.sysc_flags = (SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
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SYSC_HAS_AUTOIDLE),
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.idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
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.sysc_fields = &omap_hwmod_sysc_type1,
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};
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struct omap_hwmod_class omap2_rfbi_hwmod_class = {
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.name = "rfbi",
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.sysc = &omap2_rfbi_sysc,
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};
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/*
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* 'venc' class
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* video encoder
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*/
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struct omap_hwmod_class omap2_venc_hwmod_class = {
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.name = "venc",
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};
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/* Common DMA request line data */
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struct omap_hwmod_dma_info omap2_uart1_sdma_reqs[] = {
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{ .name = "rx", .dma_req = OMAP24XX_DMA_UART1_RX, },
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{ .name = "tx", .dma_req = OMAP24XX_DMA_UART1_TX, },
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{ .dma_req = -1 }
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};
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struct omap_hwmod_dma_info omap2_uart2_sdma_reqs[] = {
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{ .name = "rx", .dma_req = OMAP24XX_DMA_UART2_RX, },
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{ .name = "tx", .dma_req = OMAP24XX_DMA_UART2_TX, },
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{ .dma_req = -1 }
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};
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struct omap_hwmod_dma_info omap2_uart3_sdma_reqs[] = {
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{ .name = "rx", .dma_req = OMAP24XX_DMA_UART3_RX, },
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{ .name = "tx", .dma_req = OMAP24XX_DMA_UART3_TX, },
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{ .dma_req = -1 }
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};
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struct omap_hwmod_dma_info omap2_i2c1_sdma_reqs[] = {
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{ .name = "tx", .dma_req = OMAP24XX_DMA_I2C1_TX },
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{ .name = "rx", .dma_req = OMAP24XX_DMA_I2C1_RX },
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{ .dma_req = -1 }
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};
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struct omap_hwmod_dma_info omap2_i2c2_sdma_reqs[] = {
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{ .name = "tx", .dma_req = OMAP24XX_DMA_I2C2_TX },
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{ .name = "rx", .dma_req = OMAP24XX_DMA_I2C2_RX },
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{ .dma_req = -1 }
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};
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struct omap_hwmod_dma_info omap2_mcspi1_sdma_reqs[] = {
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{ .name = "tx0", .dma_req = 35 }, /* DMA_SPI1_TX0 */
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{ .name = "rx0", .dma_req = 36 }, /* DMA_SPI1_RX0 */
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{ .name = "tx1", .dma_req = 37 }, /* DMA_SPI1_TX1 */
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{ .name = "rx1", .dma_req = 38 }, /* DMA_SPI1_RX1 */
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{ .name = "tx2", .dma_req = 39 }, /* DMA_SPI1_TX2 */
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{ .name = "rx2", .dma_req = 40 }, /* DMA_SPI1_RX2 */
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{ .name = "tx3", .dma_req = 41 }, /* DMA_SPI1_TX3 */
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{ .name = "rx3", .dma_req = 42 }, /* DMA_SPI1_RX3 */
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{ .dma_req = -1 }
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};
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struct omap_hwmod_dma_info omap2_mcspi2_sdma_reqs[] = {
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{ .name = "tx0", .dma_req = 43 }, /* DMA_SPI2_TX0 */
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{ .name = "rx0", .dma_req = 44 }, /* DMA_SPI2_RX0 */
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{ .name = "tx1", .dma_req = 45 }, /* DMA_SPI2_TX1 */
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{ .name = "rx1", .dma_req = 46 }, /* DMA_SPI2_RX1 */
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{ .dma_req = -1 }
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};
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struct omap_hwmod_dma_info omap2_mcbsp1_sdma_reqs[] = {
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{ .name = "rx", .dma_req = 32 },
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{ .name = "tx", .dma_req = 31 },
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{ .dma_req = -1 }
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};
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struct omap_hwmod_dma_info omap2_mcbsp2_sdma_reqs[] = {
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{ .name = "rx", .dma_req = 34 },
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{ .name = "tx", .dma_req = 33 },
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{ .dma_req = -1 }
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};
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struct omap_hwmod_dma_info omap2_mcbsp3_sdma_reqs[] = {
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{ .name = "rx", .dma_req = 18 },
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{ .name = "tx", .dma_req = 17 },
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{ .dma_req = -1 }
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};
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/* Other IP block data */
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/*
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* omap_hwmod class data
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*/
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struct omap_hwmod_class l3_hwmod_class = {
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.name = "l3"
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};
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struct omap_hwmod_class l4_hwmod_class = {
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.name = "l4"
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};
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struct omap_hwmod_class mpu_hwmod_class = {
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.name = "mpu"
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};
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struct omap_hwmod_class iva_hwmod_class = {
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.name = "iva"
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};
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/* Common MPU IRQ line data */
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struct omap_hwmod_irq_info omap2_timer1_mpu_irqs[] = {
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{ .irq = 37, },
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{ .irq = -1 }
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};
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struct omap_hwmod_irq_info omap2_timer2_mpu_irqs[] = {
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{ .irq = 38, },
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{ .irq = -1 }
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};
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struct omap_hwmod_irq_info omap2_timer3_mpu_irqs[] = {
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{ .irq = 39, },
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{ .irq = -1 }
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};
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struct omap_hwmod_irq_info omap2_timer4_mpu_irqs[] = {
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{ .irq = 40, },
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{ .irq = -1 }
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};
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struct omap_hwmod_irq_info omap2_timer5_mpu_irqs[] = {
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{ .irq = 41, },
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{ .irq = -1 }
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};
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struct omap_hwmod_irq_info omap2_timer6_mpu_irqs[] = {
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{ .irq = 42, },
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{ .irq = -1 }
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};
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struct omap_hwmod_irq_info omap2_timer7_mpu_irqs[] = {
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{ .irq = 43, },
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{ .irq = -1 }
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};
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struct omap_hwmod_irq_info omap2_timer8_mpu_irqs[] = {
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{ .irq = 44, },
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{ .irq = -1 }
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};
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struct omap_hwmod_irq_info omap2_timer9_mpu_irqs[] = {
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{ .irq = 45, },
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{ .irq = -1 }
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};
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struct omap_hwmod_irq_info omap2_timer10_mpu_irqs[] = {
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{ .irq = 46, },
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{ .irq = -1 }
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};
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struct omap_hwmod_irq_info omap2_timer11_mpu_irqs[] = {
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{ .irq = 47, },
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{ .irq = -1 }
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};
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struct omap_hwmod_irq_info omap2_uart1_mpu_irqs[] = {
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{ .irq = INT_24XX_UART1_IRQ, },
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{ .irq = -1 }
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};
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struct omap_hwmod_irq_info omap2_uart2_mpu_irqs[] = {
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{ .irq = INT_24XX_UART2_IRQ, },
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{ .irq = -1 }
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};
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struct omap_hwmod_irq_info omap2_uart3_mpu_irqs[] = {
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{ .irq = INT_24XX_UART3_IRQ, },
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{ .irq = -1 }
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};
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struct omap_hwmod_irq_info omap2_dispc_irqs[] = {
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{ .irq = 25 },
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{ .irq = -1 }
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};
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struct omap_hwmod_irq_info omap2_i2c1_mpu_irqs[] = {
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{ .irq = INT_24XX_I2C1_IRQ, },
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{ .irq = -1 }
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};
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struct omap_hwmod_irq_info omap2_i2c2_mpu_irqs[] = {
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{ .irq = INT_24XX_I2C2_IRQ, },
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{ .irq = -1 }
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};
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struct omap_hwmod_irq_info omap2_gpio1_irqs[] = {
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{ .irq = 29 }, /* INT_24XX_GPIO_BANK1 */
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{ .irq = -1 }
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};
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struct omap_hwmod_irq_info omap2_gpio2_irqs[] = {
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{ .irq = 30 }, /* INT_24XX_GPIO_BANK2 */
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{ .irq = -1 }
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};
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struct omap_hwmod_irq_info omap2_gpio3_irqs[] = {
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{ .irq = 31 }, /* INT_24XX_GPIO_BANK3 */
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{ .irq = -1 }
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};
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struct omap_hwmod_irq_info omap2_gpio4_irqs[] = {
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{ .irq = 32 }, /* INT_24XX_GPIO_BANK4 */
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{ .irq = -1 }
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};
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struct omap_hwmod_irq_info omap2_dma_system_irqs[] = {
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{ .name = "0", .irq = 12 }, /* INT_24XX_SDMA_IRQ0 */
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{ .name = "1", .irq = 13 }, /* INT_24XX_SDMA_IRQ1 */
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{ .name = "2", .irq = 14 }, /* INT_24XX_SDMA_IRQ2 */
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{ .name = "3", .irq = 15 }, /* INT_24XX_SDMA_IRQ3 */
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{ .irq = -1 }
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};
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struct omap_hwmod_irq_info omap2_mcspi1_mpu_irqs[] = {
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{ .irq = 65 },
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{ .irq = -1 }
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};
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struct omap_hwmod_irq_info omap2_mcspi2_mpu_irqs[] = {
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{ .irq = 66 },
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{ .irq = -1 }
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};
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struct omap_hwmod_class_sysconfig omap2_hdq1w_sysc = {
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.rev_offs = 0x0,
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.sysc_offs = 0x14,
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.syss_offs = 0x18,
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.sysc_flags = (SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE |
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SYSS_HAS_RESET_STATUS),
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.sysc_fields = &omap_hwmod_sysc_type1,
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};
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struct omap_hwmod_class omap2_hdq1w_class = {
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.name = "hdq1w",
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.sysc = &omap2_hdq1w_sysc,
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.reset = &omap_hdq1w_reset,
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};
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struct omap_hwmod_irq_info omap2_hdq1w_mpu_irqs[] = {
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{ .irq = 58, },
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{ .irq = -1 }
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};
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